Flash memory with reduced size and method for accessing the same
AssigneeHynix Semiconductor Inc.
InventorSok Lee
Life of this patent
Estimating the term…
Abstract
A flash memory device is provided with reduced size and method of accessing the same. In the flash memory device, since memory cells are each coupled to a plurality of bitline pairs and is configured to be accessed by a single page buffer circuit and a single Y-gate circuit, it is possible to reduce the number of the Y-gate circuits and thereby to shrink down the size of the flash memory device.
Claims21
A flash memory device comprising:
- a memory cell array including memory cells connected to pluralities of bitlines;
- page buffer circuits correspondingly connected to bitline pairs with a predetermined number among the plural bitlines, sequentially storing sensing data bits corresponding to read data bits received through at least a portion of the bitline pairs with the predetermined number in response to one of transfer control signals and a latch control signal during a read operation, and sequentially outputting the stored data bits to one of internal input/output lines in response to one of the transfer control signals;
- Y-gate circuits correspondingly connected to the page buffers through the internal input/output lines, each connecting or disconnecting one of the internal input/output lines with a data input/output line in response to one of input/output control signals;
- and
- a Y-decoder generating the transfer control signals and the input/output control signals in response to column address signals, a read command or a program command.
The flash memory device as set forth in claim wherein each of the input/output control circuit comprises:
- a first logic circuit to output logic signals in response to one of the column address signals;
- and
- a second logic circuit to output one of the input/output control signals in response to one bit of the transfer control signals, one of the enable control signals, and the logic signals.
A method for controlling a read operation of a flash memory device, the method comprising:
- sequentially storing sensing data bits, corresponding to read data bits received through part of bitline pairs with a predetermined number, into page buffer circuits correspondingly coupled to bitlines with the predetermined number, in response to a read command;
- isolating internal input/output lines from data input/output lines by Y-gate circuits each coupled to page buffer circuits through the internal input/output lines while storing the sensing data bits each in the page buffer circuits;
- coupling the internal input/output lines to the data input/output line one by one in sequence by the Y-gate circuits after storing the sensing data bits each into the page buffer circuits;
- and
- outputting the sensing data bits, which are stored in one of the page buffer circuits, in sequence to the internal input/output line coupled to the data input/output line whenever the internal input/output lines are each coupled to the data input/output line.
A method for controlling a program operation of a flash memory device, the method comprising:
- coupling internal input/output lines to a data input/output line one by one in sequence for a predetermined time, in response to a program command, by Y-gate circuits coupled to page buffer circuits through the internal input/output lines, the page buffer circuits each coupled to bitline pairs with a predetermined number;
- sequentially storing program data bits into one of the page buffer circuits whenever one of the internal input/output lines is connected to the data input/output line;
- isolating internal input/output lines from data input/output lines by the Y-gate circuits while storing the sensing data bits in the page buffer circuits;
- and
- simultaneously outputting the program data bits, which are each stored in the page buffer circuits, to part of the bitline pairs with the predetermined number, after the isolation.
Dependencies are inferred from the claim text.