System and method for re-ordering memory references for access to memory
AssigneesMassachusetts Institute of Technology, The Board of Trustees of the Leland Stanford Junior University
InventorsWilliam Dally, Scott Rixner
Life of this patent
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Abstract
A memory processing approach involves implementation of memory status-driven access. According to an example embodiment, addresses received at an address buffer are processed for access to a memory relative to an active location in the memory. Addresses corresponding to an active location in the memory array are processed prior to addresses that do not correspond to an active location. Data is read from the memory to a read buffer and ordered in a manner commensurate with the order of received addresses at the address buffer (e.g., thus facilitating access to the memory in an order different from that received at the address buffer while maintaining the order from the read buffer).
Claims22
A computer arrangement that receives addresses corresponding to data in an order, the computer arrangement comprising:
- an address buffer that receives addresses in said order;
- a control circuit that selects, as a function of an active location in a memory and independent of any data previously provided with the addresses by the computer arrangement to convey the addresses priority and purpose, a memory reference corresponding to at least one of the received addresses, the memory reference being selected to access the memory in an order different than the order in which the addresses were received by the address buffer;
- and
- a read buffer that receives data read out from the memory.
For use by a computer arrangement, a system for accessing memory having a state of data accessibility subject to changing, the system comprising:
- a means for receiving a plurality of memory access requests in a first order;
- a means for buffering the plurality of memory access requests;
- a means for initiating an out of order memory access request to a memory array for one of the plurality of memory access requests as a function of an active location in the memory array and independent of any prioritization data previously provided with the memory access requests by the computer arrangement to convey the addresses priority and purpose;
- and
- a means for buffering memory data corresponding to the initiated memory access requests.
For use with a computer arrangement, a memory system that receives addresses corresponding to data, the memory system comprising:
- a first address buffer that receives addresses in a first order;
- a memory array;
- a second address buffer that receives data from the memory array;
- a control circuit that prioritizes the received addresses, as a function of an active location in the memory array, before the received addresses are used to access the memory array, that uses the received addresses to access the memory array, the memory array data being accessed in a second order that is different from the first order, and that provides the received data from the memory array in the first order.
Dependencies are inferred from the claim text.