Semiconductor memory device and core layout thereof

A semiconductor memory device comprising:

• a memory cell block including n global word lines;
• m sub word lines for each of the global word lines, wherein one of the sub word lines is selected in response to an activated global word line among the global word lines, j-bit first address signals and k-bit second address signals;
• and
• a word line driving unit, corresponding to the memory cell block, which drives the sub word lines, and which includes n×m word line driving circuits which maintain non-selected sub word lines at a first voltage and a selected sub word line at a second voltage,
• wherein j, k, m and n are natural numbers.

A semiconductor memory device comprising:.

• a plurality of memory cell blocks each including n global word lines and corresponding m sub word lines for each of the n global word lines, wherein one of the sub word lines is selected in response to an activated global word line among the global word lines, j-bit first address signals and k-bit second address signals;
• a plurality of word line driving units, respectively corresponding to the memory cell blocks, which drive the sub word lines inside the memory cell blocks, and including n×m word line driving circuits which maintain non-selected sub word lines at a first voltage and a selected sub world line at a second voltage;
• and
• a first decoding unit which decodes the first address signals and the second address signals and applies the first and second address signals to the word line driving unit,
• wherein j, k, m and n are natural numbers and j×k=m.