Bitline driving circuit in semiconductor memory device and driving method thereof
AssigneeHynix Semiconductor Inc.
InventorJong-Won Lee
Life of this patent
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Abstract
There is provided a bitline driving circuit and its driving method for minimizing a leakage current flowing between a wordline and a bitline in a power down mode and a self-refresh mode. The bitline driving circuit for reducing a leakage current in a semiconductor memory device includes a main driving block for precharging a bitline pair connected to a sense amplifier with a same voltage level, controlled by a main bitline equalizing signal; a sub driving block for equalizing a voltage level of a bitline pair connected to a cell array voltage in a precharge mode, controlled by a sub bitline equalizing signal; and a bitline isolation block for electrically disconnecting the main driving block and the sub driving block, controlled by a bitline isolation signal.
Claims16
A bitline driving circuit for reducing a leakage current in a semiconductor memory device, comprising:
- a main driving block for precharging a bitline pair connected to a sense amplifier with a same voltage level, controlled by a main bitline equalizing signal;
- a sub driving block for equalizing a voltage level of a bitline pair connected to a cell array voltage in a precharge mode, controlled by a sub bitline equalizing signal;
- and
- a bitline isolation block for electrically disconnecting the main driving block and the sub driving block, controlled by a bitline isolation signal.
A method for driving a bitline, comprising the steps of:
- a) precharging a bitline pair connected to a sense amplifier with a same voltage level in a power down mode or a self-refresh mode, controlled by a main bitline equalizing signal;
- b) applying the same voltage level to a bitline pair connected to a cell array in a precharge mode, controlled by a sub bitline equalizing signal;
- and
- c) electrically disconnecting the bitline pair connected to the sense amplifier and the bitline pair connected to the cell array, controlled by a bitline isolation signal.
A semiconductor memory device, configured with a plurality of cell array blocks and a plurality of sense amplifiers for amplifying a readout data from the plurality of the cell array blocks for reducing a leakage current in the semiconductor memory device, comprising:
- a main driving block for precharging a bitline pair connected to the plurality of the sense amplifiers with a same voltage level, controlled by a main bitline equalizing signal;
- and
- a sub driving block for equalizing a voltage level of a bitline pair connected to the plurality of cell array blocks in a precharge mode, controlled by a sub bitline equalizing signal;
- a bitline isolation block for electrically disconnecting the main driving block and the sub driving block, controlled by a bitline isolation signal,
- wherein the sub driving block in the other cell array block among the plurality of the cell array blocks except the cell array block selected for a refresh operation is turned off so that the bitline pair is electrically isolated from cells of the other cell array block in the self-refresh mode, controlled by the sub bitline equalizing signal.
A method for driving a bitline in a semiconductor memory device, the semiconductor memory device being configured with a plurality of cell array blocks and a plurality of sense amplifiers for amplifying a readout data from the plurality of the cell array blocks for reducing a leakage current in the semiconductor memory device, comprising the steps of:
- a) precharging a bitline pair connected to a sense amplifier to a same voltage level in a self-refresh mode, controlled by a main bitline equalizing signal;
- b) turning off the sub driving block in the other cell array block among the plurality of the cell array blocks except the cell array block selected for a refresh operation, wherein the sub driving block is controlled by a sub bitline equalizing signal in the self-refresh mode;
- and
- c) electrically disconnecting the bitline pair and a cell in the other cell array block, controlled by a bitline isolation signal.
Dependencies are inferred from the claim text.