Power saving refresh scheme for DRAMs with segmented word line architecture
AssigneeInfineon Technologies AG
InventorWolfgang Hokenmaier
Life of this patent
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Abstract
Techniques and apparatus that may be utilized to reduce current consumption during refresh cycles of DRAM devices that utilize wordline segments are provided. Rather than activate and subsequently de-activate (pre-charge) a master wordline each time a corresponding wordline segment is refreshed, the master wordline may remain activated while corresponding wordline segments are refreshed.
Claims27
A method for refreshing memory cells accessed via wordline segments driven by master wordlines, comprising:
- activating a master wordline in response to a refresh signal;
- and
- prior to de-activating the master wordline, sequentially activating a plurality of wordline segments driven by the master wordline to refresh memory cells connected thereto.
A method for refreshing memory cells accessed via wordline segments driven by master wordlines, comprising:
- (a) activating a master wordline selected based on an internally generated refresh address;
- (b) prior to de-activating the selected master wordline, activating a plurality of wordline segments driven by the master wordline to refresh memory cells connected thereto;
- (c) de-activating the master wordline;
- (d) adjusting the refresh address;
- and
- (e) repeating steps (a)-(c) to refresh memory cells connected to wordline segments driven by other master wordlines.
A memory device, comprising:
- a plurality of memory cells connected to wordline segments driven by master wordlines;
- and
- refresh circuitry configured to activate a master wordline in response to a refresh signal and, prior to de-activating the master wordline, sequentially activate a plurality of wordline segments driven by the master wordline to refresh memory cells connected thereto.
A memory device, comprising:
- a plurality of memory cells connected to wordline segments driven by master wordlines;
- refresh circuitry configured to:
- (a) activate a master wordline selected based on an internally generated refresh address;
- (b) prior to de-activating the selected master wordline, activate a plurality of wordline segments driven by the master wordline to refresh memory cells connected thereto;
- (c) de-activate the master wordline;
- (d) adjust the refresh address;
- and
- (e) repeat steps (a)-(c) to refresh memory cells connected to wordline segments driven by other master wordlines.
A dynamic random access memory (DRAM) device, comprising:
- a plurality of master wordlines;
- a plurality of wordline segments driven by the master wordlines, each having a plurality of memory cells connected thereto;
- and
- refresh circuitry configured to refresh each of the memory cells during a device refresh cycle during which each of the master wordlines is only activated once to refresh memory cells connected to wordline segments driven thereby.
A method for refreshing memory cells accessed via wordline segments driven by master wordlines, comprising:
- in response to a first refresh command, activating a master wordline, activating and de-activating a first wordline segment driven by the master wordline;
- in response a second one or more refresh commands, activating and de-activating a corresponding second one or more wordline segments driven by the master wordline prior to prior to de-activating the master wordline;
- and
- in response to a third refresh command, activating and de-activating a third wordline segment driven by the master wordline and de-activating the master wordline.
A memory device, comprising:
- a plurality of memory cells connected to wordline segments driven by master wordlines;
- and
- means for activating a master wordline in response to a refresh signal and, prior to de-activating the master wordline, sequentially activating a plurality of wordline segments driven by the master wordline to refresh memory cells connected thereto.
Dependencies are inferred from the claim text.