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US 2006/0215472 A1Published application
Memory device having shared open bit line sense amplifier architecture
AssigneeSamsung Electronics Co., Ltd.
InventorsJae-Man Yoon, Choong-Ho Lee, Dong-Gun Park, Yeong-Taek Lee, Chul Lee
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Abstract
Provided is a memory device with a shared open bit line sense amplifier architecture. The memory device includes memory cell arrays, each memory cell array including bit lines, and a sense amplifier configured to couple to at least two bit lines a memory cell array and configured to couple to at least two bit lines of a different memory cell array.
Claims20
A memory device comprising:
- at least two memory cell arrays, each memory cell array including a plurality of bit lines;
- and
- at least one sense amplifier, each sense amplifier configured to couple to at least two bit lines of one of the memory cell arrays and configured to couple to at least two bit lines of a different one of the memory cell arrays.
A memory device comprising:
- first through third memory cell arrays, each memory cell array including at least four bit lines;
- a first sense amplifier configured to couple to at least two bit lines of the first memory cell array and configured to couple to at least two bit lines of the second memory cell array;
- and
- a second sense amplifier configured to couple to a different at least two bit lines of the second memory cell array and configured to couple to at least two bit lines of the third memory cell array.
1 more element
A method of operating a memory device, comprising:
- selecting a pair of bit lines from at least four bit lines coupled to a sense amplifier;
- and
- sensing the pair of bit lines using the sense amplifier.
Dependencies are inferred from the claim text.