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US 2006/0215471 A1Published application
Single transistor sensing and double transistor sensing for flash memory
AssigneeSilicon Storage Technology, Inc.
InventorHieu Tran
Life of this patent
Estimating the term…
Abstract
A single sensing transistor is selectively diode connected to a sense line that is coupled to reference cells and data cells to store a reference current or leakage currents on the gate of the sensing transistor by opening the switch to disconnect the diode connection of the sensing transistor. Other sensing systems may use two transistors and may stores leakage current. A sensing system with capacitance auto-zeroing is included. The sensing system may include a dynamic differential current differential amplifier.
Claims54
A sensing system for a memory comprising:
- a transistor coupled between a voltage terminal and a sense line, said sense line being selectively coupled to a reference cell terminal in a first mode, and to a data cell terminal in a second mode;
- and
- a switch coupled between the sense line and a bias terminal of said transistor to selectively couple the sense line to the bias terminal in the first mode and to uncouple the bias terminal from the sense line in the second mode.
A sensing system for a memory comprising:
- a transistor coupled between a voltage terminal and a sense line, said sense line being selectively coupled to a reference cell terminal in a first mode, and to a data cell terminal in a second mode;
- and
- a switch coupled between the sense line and a bias terminal of said transistor to selectively couple the sense line to the bias terminal in the second mode and to uncouple the bias terminal from the sense line in the first mode, wherein said sensing line is selectively coupled to a plurality of reference cell terminals in a serial manner in the second mode.
A sensing system for a memory comprising:
- a first transistor coupled between a voltage terminal and a sense line, said sense line being selectively coupled to a reference cell terminal in a first mode and to a data cell terminal in a second mode;
- a first switch coupled between the sense line and a bias terminal of said first transistor to selectively couple the sense line to the bias terminal in the first mode and to uncouple the bias terminal from the sense line in the second mode;
- a second transistor coupled between the sense line and a ground terminal;
- a second switch coupled between the sense line and the second transistor to selectively couple the sense line to the second transistor in the second mode and a third mode and uncouple the sense line from the second transistor in the first mode;
- and
- a third switch coupled between the second switch and a bias terminal of said second transistor to selectively couple the second switch to the bias terminal in the second mode and to uncouple the bias terminal from the second switch in the third mode.
3 more elements
A sensing system for memory comprising:
- a first transistor coupled between a voltage terminal and a sense line, said sense line being selectively coupled to a reference cell terminal and to a data cell terminal;
- a first switch coupled between the sense line and the bias terminal of said first transistor to selectively couple the sense line to the bias terminal;
- a second transistor coupled between the voltage terminal and a sense line;
- and
- a second switch coupled between the sense line and bias terminal of said second transistor to selectively couple the sense line to said bias terminals,
- wherein in a first mode the first switch selectively couples and uncouples a reference cell terminal coupled to a reference cell in an unselected state, in a second mode said second switch selectively couples the bias terminal of the second transistor to the sense line and to the reference cell terminal that is coupled to the reference cell in a selected state, in a third mode the first switch selectively couples and uncouples the bias terminal of the first transistor to a data cell terminal that is coupled to a data cell in an selected state, and in a fourth mode the first and second switches uncouple the bias terminals of the respective first and second transistors from the sensing line and the sensing line is coupled to the data cell terminal which is coupled to the data cell in a selected state.
3 more elements
A sensing system for a memory comprising;
- a first transistor coupled between a voltage terminal and a sense line, said sense line being selectively coupled to a reference cell terminal;
- a first switch coupled between the sense line and a bias terminal of said transistor to selectively couple the sense line to the bias terminal in a first mode during which a reference cell coupled to the reference cell terminal is in an unselected state to apply a leakage current to said bias terminal, to uncouple the bias terminal from the sense line in second and third modes, and to selectively couple the sense line to the bias terminal in a fourth mode to apply a leakage current and a reference cell current from a reference cell in a selected state;
- a second transistor coupled between the sense line and a ground terminal;
- a second switch coupled between the sense line and the second terminal to selectively couple the sense line to the second terminal in the second and fourth modes and uncouple the sense line from the second transistor in the first and third modes;
- and
- a third switch coupled between the second switch and a bias terminal of said second terminal to selectively couple the second switch to the bias terminal in the second mode and to uncouple the bias terminal from the second switch in the third and fourth modes.
3 more elements
A sensing system for a memory comprising:
- a transistor coupled between a voltage terminal and a reference cell terminal;
- a current source;
- a first switch coupled between the reference cell terminal and a bias terminal of said transistor to selectively couple the reference cell terminal to the bias terminal in a first mode and to uncouple the bias terminal from the reference cell terminal in a second mode;
- and
- a second switch coupled between the reference cell terminal and the current souse to selectively couple the current source to the reference cell terminal in the second mode and to uncouple the bias terminal from the reference cell terminal in the first mode, wherein a reference cell coupled to the reference cell terminal is unselected in the first mode and is selected in the second mode.
2 more elements
A sensing system for memory comprising:
- an operational amplifier including first and second inputs and including an output;
- a first transistor coupled between a voltage terminal and the first input, said first input being selectively coupled to a reference cell terminal;
- a first switch coupled between the first input and the bias terminal of said first transistor to selectively couple the first input to the bias terminal;
- a second transistor arranged in a diode configuration;
- a second switch coupled between the second transistor and the first input, said second transistor between the voltage terminal and the second switch;
- a third transistor coupled between the voltage terminal and the second input, said second input being selectively coupled to a data cell terminal;
- a third switch coupled between the second input and the bias terminal of said third transistor to selectively couple the second input to the bias terminal;
- a fourth transistor arranged in a diode configuration;
- a fourth switch coupled between the fourth transistor and the second input, said fourth transistor between the voltage terminal and the fourth switch;
- wherein in a first mode the first switch selectively couples and uncouples the reference cell terminal coupled to a reference cell in an unselected state,
- wherein in a second mode the third switch selectively couples and uncouples the data cell terminal coupled to a data cell in an unselected state,
- wherein in a third mode said second switch selectively couples the second transistor to the first input, said fourth switch selectively couples the fourth transistor to the second input, and the reference cell and the data cell are in a selected state.
9 more elements
A sensing system for a memory comprising:
- a cancellation circuit to generate a cancellation signal to offset a leakage current on a memory cell line;
- a pull-up load selectively coupled to the memory cell line;
- and
- a differential amplifier coupled to the memory cell line and the circuit.
1 more element
A serial sensing system for a memory comprising:
- a cancellation circuit to generate a cancellation signal to offset a leakage current on a memory cell line;
- and
- a differential amplifier coupled to the memory cell line and the circuit.
A sensing system for a memory comprising:
- a cancellation circuit to detect and cancel capacitance mismatch on a reference memory cell bitline and a data memory cell bitline;
- a bias circuit selectively coupled to a reference memory cell terminal and to a data memory cell terminal, the reference memory cell terminal and the data memory cell terminal being selectively coupled to the reference memory cell bitline and the data memory cell bitline.
A method of sensing a memory comprising:
- detecting capacitance mismatch on a first memory cell bitline and a second memory cell bitine;
- and
- canceling said capacitance mismatch.
The method of 45 further comprising comparing voltages in an autozero mode.
The method of 44 further comprising autozeroing the bitlines prior to said comparing.
A sensing system for a memory comprising:
- a first differential current source generating a first differential current in response to a reference current sensed on a reference memory cell line relative to a data current sensed on a data memory cell line;
- a second differential current source generating a differential current in response to the data current sensed on the data memory cell line relative to reference current sensed on the reference memory cell line;
- and
- a differential voltage amplifier including &first and second inputs coupled to the first and second differential current sources, respectively.
1 more element
Dependencies are inferred from the claim text.