Semiconductor memory device
AssigneeSharp Kabushiki Kaisha
InventorsShinsuke Anzai, Masahiko Watanabe, Takahiko Yoshimoto
Life of this patent
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Abstract
In a semiconductor memory device for reading out multilevel data in a time-shared manner at different timings, by providing plural control signal lines for controlling the operation timings of the output buffer circuits, the operation timings of output buffer circuits can be displaced, and the number of output buffer circuits operating simultaneously can be decreased, with the result that noise is reduced. Besides, by allowing the output buffer circuit, which outputs data read out early in a time-shared manner, to operate at an early timing, data output is terminated without retarding the operation timing of the output buffer circuit operating at the last timing.
Claims7
A semiconductor memory device comprising:
- a memory cell capable of storing data of plural bits;
- a sense amplifier for reading the data out from the memory cell in plural times of sensing operations at different timings;
- plural output buffer circuits for outputting individually the sensed data detected by the respective sensing operations of the sense amplifier;
- and
- a control circuit for controlling the operation timing of the output buffer circuits, wherein
- the control circuit has plural different control signal lines for controlling the operation timings of the output buffer circuits.
Dependencies are inferred from the claim text.