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US 2006/0215467 A1Published application
Method of increasing data setup and hold margin in case of non-symmetrical PVT
OwnerTorsten Partschinventor
Life of this patent
Estimating the term…
Abstract
Techniques and apparatus to reduce duty cycle distortion in DRAM devices caused by process variations are provided. By dividing the undelayed output signal from the data receivers into two separate paths and providing independently adjustable delay blocks in each path leading to the rising and falling edge data latches, the setup and/or hold timing margins may be adjusted.
Claims21
A memory device, comprising:
- a plurality of data pads for receiving data signals transmitted on rising and falling edges of an externally supplied data strobe signal;
- and
- for each data pad, a receive and latch circuit having a receiver circuit to receive data signals provided on the data pad, a first delay element in a signal path between the receiver circuit and a first latch circuit to delay, by a first delay amount, a first data signal latched by the first latch circuit on a rising edge of the data strobe signal, and a second delay element in a signal path between the receiver circuit and a second latch circuit to delay, by a second delay amount, a second data signal latched by the second latch circuit on a rising edge of the data strobe signal.
The memory device of claim 3, wherein the first and second delay amounts are independently adjustable during manufacturing of the device by altering connections made via one or more metal layers of components forming the first and second delay elements.
A double data rate (DDR) dynamic random access memory (DRAM) device, comprising:
- a plurality of data pads for receiving data signals transmitted on rising and falling edges of an externally supplied data strobe signal;
- and
- for each data pad, a receive and latch circuit having,
- a receiver circuit to receive data signals provided on the data pad,
- a first latch circuit to latch a first data signal received by the receiver circuit in conjunction with a rising edge of the data strobe signal,
- a second latch circuit to latch a second data signal received by the receiver circuit in conjunction with a falling edge of the data strobe signal,
- a first delay element in a signal path between the receiver circuit and the first latch circuit to delay the first data signal by a first delay amount, and
- a second delay element in a signal path between the receiver circuit and the second latch circuit to delay the second data signal by a second delay amount, wherein the first and second delay amounts are independently adjustable.
5 more elements
A receive and latch circuit, comprising:
- a receiver circuit to receive data signals provided on a data pad;
- a first latch circuit to latch a first data signal received by the receiver circuit in conjunction with a rising edge of a data strobe signal;
- a second latch circuit to latch a second data signal received by the receiver circuit in conjunction with a falling edge of the data strobe signal;
- a first delay element in a signal path between the receiver circuit and the first latch circuit to delay the first data signal by a first delay amount;
- and
- a second delay element in a signal path between the receiver circuit and the second latch circuit to delay the second data signal by a second delay amount, wherein the first and second delay amounts are independently adjustable.
3 more elements
A method for adjusting setup and hold data sampling times in a memory device for process variations, comprising:
- receiving a data strobe signal;
- delaying a first data signal sent in conjunction with a rising edge of the data strobe signal by a first delay amount;
- delaying a second data signal sent in conjunction with a falling edge of the data strobe signal by a second delay amount independent of the first delay amount;
- and
- latching the first and second data signals with first and second latch circuits triggered, respectively, on rising and falling edges of the data strobe signal.
2 more elements
A method of manufacturing a memory device, comprising:
- fabricating the memory device having a plurality of data pads for receiving data signals transmitted on rising and falling edges of an externally supplied data strobe signal and, for each data pad, a receive and latch circuit having a first latch to latch a first data signal received by the receiver circuit on a rising edge of the data strobe signal and a second latch to latch a second signal received by the receiver circuit;
- performing one or more tests to determine effects of process variations on setup and hold times of data signals relative to the data strobe signal;
- and
- based on results of the one or more tests, adjusting a first delay element in a signal path between the receiver circuit and a first latch circuit and a second delay element in a signal path between the receiver circuit and a second latch circuit.
1 more element
A receive and latch circuit, comprising:
- means for receiving data signals provided on a data pad;
- means for latching a first data signal received by the means for receiving in conjunction with a rising edge of a data strobe signal;
- means for latching a second data signal received by the means for receiving in conjunction with a falling edge of the data strobe signal;
- in a signal path between the means for receiving and the means for latching the first data signal, means for delaying the first data signal by a first delay amount;
- and
- in a signal path between the means for receiving and the means for latching the second data signal, means for delaying the second data signal by a second delay amount, wherein the first and second delay amounts are independently adjustable.
3 more elements
Dependencies are inferred from the claim text.