Methods and systems for generating latch clock used in memory reading
AssigneeMediatek Incorporation
InventorJui-Hsing Tseng
Life of this patent
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Abstract
Methods and systems for generating a latch clock in memory reading. Data with a first logic level and with a second logic level are stored into a first address and a second address of a memory, respectively. A read data signal is generated by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory. A divided frequency signal is generated by dividing a frequency of the internal clock. A phase of the divided frequency signal is adjusted according to a delay parameter by varying the delay parameter until at least an edge of the divided frequency signal is aligned with any edge of the read data signal. Finally, the latch clock is generated according to the delay parameter and the internal clock.
Claims20
A method for generating, from an internal clock, a latch clock used in reading a memory, the method comprising:
- storing data with a first logic level into a first address of the memory and data with a second logic level into a second address of the memory;
- generating a read data signal by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory;
- generating a divided frequency signal by dividing a frequency of the internal clock;
- adjusting a phase of the divided frequency signal according to a delay parameter by varying the delay parameter until at least an edge of the divided frequency signal is aligned with any edge of the read data signal;
- and
- generating the latch clock according to the delay parameter and the internal clock.
A memory subsystem, comprising:
- a memory;
- and
- a memory controller comprising an internal clock, the memory controller operative in a calibration mode to store data with a first logic level into a first address of the memory, to store data with a second logic level into a second address of the memory, to generate a read data signal by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory, to generate a divided frequency signal by dividing a frequency of the internal clock, to adjust a phase of the divided frequency signal according to a delay parameter by varying the delay parameter until at least an edge of the divided frequency signal is aligned with any edge of the read data signal, and to generate a latch clock according to the delay parameter and the internal clock.
A memory subsystem, comprising:
- a memory;
- and
- a memory controller providing a latch clock and accessing the memory with reference to the latch clock, comprising:
- means for storing data with a first logic level into a first address of the memory, and storing data with a second logic level into a second address of the memory;
- means for generating a read data signal by issuing continuous read commands to repeatedly retrieve the data at the first and the second addresses of the memory;
- means for generating a divided frequency signal by dividing a frequency of an internal clock;
- means for adjusting a phase of the divided frequency signal according to a delay parameter by varying the delay parameter until at least an edge of the divided frequency signal is aligned with any edge of the read data signal;
- and
- means for generating the latch clock according to the delay parameter and the internal clock.
Dependencies are inferred from the claim text.