Memory device with a ramp-like voltage biasing structure and reduced number of reference cells

A method for operating a memory device including a plurality of memory cells, the method including the steps of:

• comparing a set of selected memory cells with at least one reference cell having a predefined threshold voltage, the step of comparing including:
• applying a biasing voltage having a substantially monotonic time pattern to the selected memory cells and the at least one reference cell,
• detecting the reaching of a comparison current by a measure cell current corresponding to each selected memory cell and by a measure reference current corresponding to each reference cell, and
• determining a condition of each selected memory cell according to a temporal relation of the reaching of the comparison current by the corresponding measure cell current and by the at least one measure reference current,
• wherein the step of comparing further includes:
• modifying at least one of said currents to emulate the comparison with at least one further reference cell having a further threshold voltage.

A read circuit operable to read a memory cell storing a data value, the circuit comprising:

• a sense amplifier operable to
• detect when a data signal from the memory cell achieves a first predetermined relationship to a first comparison signal,
• detect when a reference signal from a reference cell achieves a second predetermined relationship to a second comparison signal, and
• identify the data value stored in the memory cell by determining an order in which the data signal and reference signal respectively achieve the first and second predetermined relationships to the first and second comparison signals;
• and
• a modifier operable to modify a time at which the reference signal achieves the second predetermined relationship to the second comparison signal.

An integrated circuit, comprising:

• a memory cell operable to store a data value and to generate a data signal that represents the data value;
• a reference cell operable to generate a reference signal;
• a sense amplifier coupled to the memory and reference cells and operable to
• detect when the data signal from the memory cell achieves a first predetermined relationship to a first comparison signal,
• detect when the reference signal from the reference cell achieves a second predetermined relationship to a second comparison signal, and
• identify the data value stored in the memory cell by determining an order in which the data signal and reference signal respectively achieve the first and second predetermined relationships to the first and second comparison signals;
• and
• a modifier operable to modify a time at which the reference signal achieves the second predetermined relationship to the second comparison signal.

A system, comprising:

• an integrated circuit, comprising,
• a memory cell operable to store a data value and to generate a data signal that represents the data value;
• a reference cell operable to generate a reference signal;
• a sense amplifier coupled to the memory and reference cells and operable to
• detect when the data signal from the memory cell achieves a first predetermined relationship to a first comparison signal,
• detect when the reference signal from the reference cell achieves a second predetermined relationship to a second comparison signal, and
• identify the data value stored in the memory cell by determining an order in which the data signal and reference signal respectively achieve the first and second predetermined relationships to the first and second comparison signals;
• and
• a modifier operable to modify a time at which the reference signal achieves the second predetermined relationship to the second comparison signal.