Buffer circuit and memory system for selectively outputting data strobe signal according to number of data bits

Abstract

Provided are a buffer circuit and a memory system for selectively outputting a data strobe signal according to the number of data bits. The buffer circuit includes a first buffer unit, a second buffer unit, and a third buffer unit. The first buffer unit amplifies and outputs a first signal. The second buffer unit amplifies and outputs a second signal or outputs the first signal according to the logic level of a control signal. The third buffer unit amplifies the first signal to send or not to send the amplified first signal to the second buffer unit depending on the logic level of an inverted control signal. The logic levels of the control signal and the inverted control signal are determined according to the number of processed data bits. When the number of processed data bits is n, the control signal is set to a first level and the inverted control signal is set to a second level, and when the number of processed data bits is k, the control signal is set to a second level and the inverted control signal is set to a first level. Since the buffer circuit and the memory system selectively output the data strobe signal according to the number of data bits, a point of time when the data are latched can be advanced and a setup/hold time of the data can be reduced.

Dependencies are inferred from the claim text.