US 2006/0215460 A1 · METHOD OF OPERATING P-CHANNEL MEMORY

Abstract

A method of operating a P-channel memory is described. The P-channel memory includes a substrate, a gate formed over the substrate, a charge trapping structure disposed between the substrate and the gate, and the first and second sources/drains formed in the substrate adjacent to two sides of the charge trapping structure. An erasing operation is performed by applying a first voltage to the second source/drain, applying a second voltage to the first source/drain, applying a third voltage to the gate, and applying a forth voltage to the substrate. Hot holes are injected in the charge trapping structure to erase the P-channel memory by the tertiary hot hole mechanism. The absolute value of the voltage differential between the third and the forth voltages is equal to, or less than 6V, and the second voltage is smaller than the third voltage.

Claims20

Dependent claims

A method of operating a P-channel memory having a substrate, a gate formed over the substrate, a charge trapping structure disposed between the substrate and the gate, and a first source/drain and a second source/drain formed in the substrate adjacent two sides of the charge trapping structure, the method comprising:

performing a programming operation to inject electrons in the side of the charge trapping structure adjacent to the first source/drain to store a first bit in the P-channel memory;
and
performing an erasing operation by applying a first voltage to the second source/drain, applying a second voltage to the first source/drain, applying a third voltage to the gate, and applying a fourth voltage to the substrate to inject hot holes in the side of the charge trapping structure adjacent to the first source/drain by a tertiary hot hole mechanism to erase the first bit stored in the P-channel memory, wherein a voltage differential between the third voltage and the fourth voltage is smaller than or equal to 6V, and the second voltage is smaller than the third voltage.

A method of operating a P-channel memory, adapted for a P-channel silicon/silicon oxide/silicon nitride/silicon oxide/silicon (P-channel SONOS) memory having a P-type structure, an ONO layer formed over the substrate, a P-type doped polysilicon gate formed over the ONO layer, and a first source/drain and a second source/drain formed in the substrate adjacent to two sides of the ONO layer, the method comprising:

performing a programming operation by applying a first voltage to the second source/drain, applying a second voltage to the first source/drain, applying a third voltage to the P-type doped polysilicon gate, and applying a fourth voltage to the substrate to inject electrons in the side of the ONO layer adjacent to the first source/drain to store a first bit in the P-channel SONOS memory, wherein the second voltage is smaller than the third voltage;
and
performing an erasing operation by applying a fifth voltage to the second source/drain, applying a sixth voltage to the first source/drain, applying a seventh voltage to the gate, and applying an eighth voltage to the substrate to inject hot holes in the side of the ONO layer adjacent to the first source/drain by a tertiary hot hole mechanism to erase the first bit stored in the P-channel SONOS memory, wherein a voltage differential between the seventh voltage and the eighth voltage is smaller than or equal to 6V, the sixth voltage is smaller than the seventh voltage, and the seventh voltage is smaller than the third voltage.

Dependencies are inferred from the claim text.

Method of operating p-channel memory

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Method of operating p-channel memory

Life of this patent

Abstract

Claims20