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US 2006/0215459 A1Published application
Active and Passive Programming/Erasing Time and Verifiable Reading for Memory System
AssigneeBeedar Technology Inc.
InventorsPingFu Hsieh, KuoCheng Weng, LiangHung Wang
Life of this patent
Estimating the term…
Abstract
A new specific memory control unit design to apply program and erase function wherein use the new methodology of memory configured logic to manipulate timing parameter.
Claims4
An arrangement of erase/program time control methodology, comprising:
- a control unit operable to transmit/receive data, run algorithm, and manipulate data flow;
- a memory structure operable to store information wherein includes program/erase and read function;
- a plurality of procedure signals operable to operate functions;
- a plurality of procedure signals operable to operate functions.
1 more element
A verified methodology in the read mode, comprising the steps of:
- a check sum unit wherein contains variable check sum algorithms;
- a configuration wherein stored variable check sum commands in the memory unit;
- a counter wherein counts the iterations of check sum.
Dependencies are inferred from the claim text.