Method of generating cell library data for large scale integrated circuits

A method of extracting MOS transistor resistances for a cell constructed of interconnected MOS transistors having source and drain regions with metal silicided surfaces, the method being comprised of extracting source and drain resistances for the MOS transistors according to source and drain region surface areas by using a resistance calculating formula or referring to a resistance extraction reference file which, when the source and drain regions have surface areas with a first surface area region, treats the source and drain resistances as resistance values which depend on said surface areas, and when the source and drain regions have surface areas with a second surface area region that is larger than the first surface area region, treats the source and drain resistances as fixed resistance values which are independent of said surface areas.

A library data generating program which causes a computer to execute library data generating procedures for a cell constructed of interconnected MOS transistors having source and drain regions with metal silicided surfaces, wherein the procedures include:

• a resistance extraction procedure which extracts source and drain resistances for the MOS transistors according to source and drain region surface areas by using a resistance calculating formula or referring to a resistance extraction reference file which, when the source and drain regions have surface areas with a first surface area region, treats the source and drain resistances as resistance values which depend on said surface area, and when the source and drain regions have surface areas with a second surface area region that is larger than the first surface area region, treats the source and drain resistances as fixed resistance values which are in dependent of said surface areas;
• and
• a simulation procedure which generates an input-output characteristic for the cell from a netlist containing a MOS transistor model that includes the source and drain resistances extracted in the resistance extraction procedure and connection information for the model, and from input signals.

A MOS transistor resistance extracting program which causes a computer to execute MOS transistor resistance extracting procedures for a cell constructed of interconnected MOS transistors having source and drain regions with metal silicided surfaces, the program being comprised of the resistance extracting procedures of extracting source and drain resistances for the MOS transistors according to source and drain region surface areas by using a resistance calculating formula or referring to a resistance extraction reference file which, when the source and drain regions have surface areas with a first surface area region, treats the source and drain resistances as resistance values which depend on said surface areas, and when the source and drain regions have surface areas with a second surface area region that is larger than the first surface area region, treats the source and drain resistances as fixed resistance values which are independent of said surface areas.