Page buffer of flash memory device with improved program operation performance and program operation control method
AssigneeHynix Semiconductor Inc.
InventorJin Seong
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Abstract
TA page buffer of a flash memory device has a page buffer that improves the program operation performance and program operation control method thereof. The page buffer has a flash memory device having a MLC. The page buffer stores input data in an upper bit register, initial data having the same value as that of the input that data are stored in a lower bit register.
Claims10
A non-volatile memory device, comprising:
- a memory cell array having a plurality of Multi-Level Cells (MLCs), each MLC being configured to store at least first and second bits of data;
- a page buffer coupled to the memory cell array via at least first and second bit lines, the page buffer including:
- a bit line select unit configured to
- select one of the first and second bit lines and
- connect the selected bit line to a sense node in response to bit line select signals and discharge signals;
- an upper bit register configured to
- store upper bit sensing data and a voltage level of the sense node and output first upper bit output data in response to an upper bit read signal, or
- store first or second input data received through a data I/O terminal or
- output second upper bit output data in response to data input signals;
- and
- a lower bit register configured to
- store lower bit sensing data and output first lower bit output data in response to a lower bit read signal and the voltage level of the sense node, or
- store first or second initial data received through a latch initialization circuit or
- output second lower bit output data in response to the data input signals.
A program operation control method of a non-volatile memory device including a plurality of Multi-Level Cells (MLCs) that are each configured to store at least two bits of data, the MLCs being coupled to at least first and second bit lines, the method comprising:
- selecting one of the first and second bit lines;
- coupling the selected bit line to a sense node in response to a bit line select signal and a discharge signal;
- programming first or second initial data stored in a lower bit register into a MLC coupled to the selected bit line in response to a data input signal as lower bit data;
- and
- programming generated upper bit data into the MLC based on first or second input data input to the upper bit register in response to third or fourth initial data, the lower bit data, and the data input signal.
Dependencies are inferred from the claim text.