NROM flash memory cell with integrated DRAM
AssigneeMicron Technologies, Inc.
InventorLeonard Forbes
Life of this patent
Estimating the term…
Abstract
A memory device that is comprised of a dynamic random access memory (DRAM) capacitor and a nitride read only memory (NROM) transistor. The memory device provides multiple modes of operation including a DRAM mode using the capacitor and a non-volatile random access memory mode using the NROM transistor. The device is comprised of two source/drain regions between which a gate insulator layer is formed. A control gate, coupled to a word line, is formed on top of the gate insulator. The DRAM capacitor is coupled to one of the source/drain regions while the second source/drain region is coupled to a bit line that is eventually coupled to a sense amplifier for reading the state or states of the memory device.
Claims20
A method for operating an NROM flash memory cell having an integrated dynamic random access memory (DRAM), an NROM transistor having a control gate, and a plurality of modes, the method comprising:
- determining a mode of the memory cell;
- and
- transferring data from the DRAM to the transistor in response to a negative voltage on the control gate for a predetermined period of time.
A method for operating a memory device comprising a dynamic random access memory (DRAM) coupled to a non-volatile transistor having a nitride trapping layer and a control gate, the method comprising:
- writing data into the DRAM in response to a first potential on the control gate;
- and
- writing data into the transistor in response to a second potential on the control gate, the second potential being different than the first potential.
A memory device comprising:
- a memory array having a plurality of non-volatile memory cells having a plurality of operation modes, each memory cell comprising a DRAM and a transistor, the transistor coupled between the capacitor and a data line and acting as a transfer gate for the DRAM, the transistor comprising a control gate and a data storage layer;
- and
- control circuitry that is adapted to execute a programming operation of the memory array comprising applying a negative voltage to predetermined control gates for a predetermined period of time in response to a power-down condition of the memory device.
An electronic system comprising:
- a processor that generates control signals;
- and
- a memory device coupled to the processor and operating in response to the control signals, the device comprising:
- a memory array having a plurality of non-volatile memory cells having a plurality of operation modes, each memory cell comprising a DRAM and a transistor, the transistor coupled between the capacitor and a data line and acting as a transfer gate for the DRAM, the transistor comprising a control gate and a data storage layer;
- and
- control circuitry that is adapted to execute a programming operation of the memory array comprising applying a negative voltage to predetermined control gates for a predetermined period of time in response to a power-down condition of the memory device.
Dependencies are inferred from the claim text.