Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsMitsuaki Honma, Noboru Shibata, Kazunori Kanebako
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a memory cell array with memory cells arranged therein, each memory cell storing data defined by threshold voltage thereof, wherein the memory cell array includes first and second areas; the first area stores multi-value data written with plural write steps; and the second area stores binary data defined by first and second logic states, threshold levels of which are controlled through the plural write steps adapted to the multi-value data write.
Claims20
A semiconductor memory device comprising a memory cell array with memory cells arranged therein, each memory cell storing data defined by threshold voltage thereof, wherein
- the memory cell array includes first and second areas;
- the first area stores multi-value data written with plural write steps;
- and
- the second area stores binary data defined by first and second logic states, threshold levels of which are controlled through the plural write steps adapted to the multi-value data write.
A semiconductor memory device comprising:
- a memory cell array having word lines and bit lines disposed to intersect each other, and electrically rewritable and non-volatile memory cells disposed at crossings of the word lines and bit lines;
- a row decoder configured to selectively drive the word lines;
- and
- a sense amplifier circuit coupled to the bit lines, wherein
- the memory cell array includes first and second areas, which are defined therein as being arranged in the direction of the word lines and accessed simultaneously,
- the first area stores multi-value data written with plural write steps, and
- the second area stores binary data defined by first and second logic states, which are written through the plural write steps adapted to the multi-value data write.
Dependencies are inferred from the claim text.