Temperature compensation of thin film diode voltage threshold in memory sensing circuit

A diode threshold voltage variance compensation method, comprising:

• utilizing a sensing circuit to supply a read operation voltage to an array core, the array core comprising a thin film diode in series with a nanoscale resistive memory cell, the nanoscale resistive memory cell having a controllably conductive media between a first electrode and a second electrode;
• tracking a threshold voltage variance of the thin film diode of the array core during a read operation of the array core;
• generating a temperature compensating bias voltage based on the threshold voltage variance by a temperature sensitive bias circuit;
• and
• applying the temperature compensating bias voltage to the nanoscale resistive memory cell of the array core to maintain a constant read operation voltage level across the nanoscale resistive memory cell.

A threshold voltage variance compensation system, comprising:

• means for utilizing a sensing circuit to supply a read operation voltage to an array core, the array core comprising a thin film diode in series with a nanoscale resistive memory cell, the nanoscale resistive memory cell having a controllably conductive media between a first electrode and a second electrode;
• means for tracking a threshold voltage variance of the thin film diode of the array core during a read operation of the array core;
• means for generating a temperature compensating bias voltage based on the threshold voltage variance by a temperature sensitive bias circuit;
• and
• means for applying the temperature compensating bias voltage to the nanoscale resistive memory cell of the array core for maintaining a constant read operation voltage level across the nanoscale resistive memory cell.

A memory cell operation voltage system, comprising:

• a sensing circuit to provide an operation voltage to a memory array, the memory array comprising at least one first temperature variable select device in series with a nanoscale resistive memory cell, the nanoscale resistive memory cell having a controllably conductive media between a first electrode and a second electrode;
• a reference circuit to produce a reference temperature compensating bias voltage to maintain a constant operation voltage level within the nanoscale resistive memory cell;
• and
• a differential amplifier to duplicate the reference temperature compensating bias voltage to the nanoscale resistive memory cell of the memory array.