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US 2006/0214901 A1Published application
Semiconductor circuit, display device, electronic apparatus
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorShuhei Nagatsuka
Life of this patent
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Abstract
To provide a semiconductor circuit having D flip-flops, a display device and an electronic apparatus having the display device, in the invention, the number of transistors is reduced by using 2 n-channel transistors and 2 p-channel transistors instead of using 2 conventional clocked inverters that have a total of 8 transistors in D flip-flops.
Claims42
A semiconductor circuit characterized by comprising:
- a first n-channel transistor, a first p-channel transistor, a second n-channel transistor, a second p-channel transistor, and an inverter circuit, comprising:
- a gate terminal of the first n-channel transistor and a gate terminal of the first p-channel transistor to which a first input signal is inputted;
- a first terminal of the first n-channel transistor to which a timing control signal is inputted;
- a first terminal of the first p-channel transistor to which an inverted timing control signal is inputted;
- a second terminal of the first n-channel transistor, and a second terminal of the first p-channel transistor electrically connected to the second terminal of the first n-channel transistor;
- wherein the second terminal of the first n-channel transistor and the second terminal of the first p-channel transistor are electrically connected to an input terminal of the inverter circuit;
- a gate terminal of the second n-channel transistor and a gate terminal of the second p-channel transistor to which a second signal that is outputted from an output terminal of the inverter circuit is inputted;
- a first terminal of the second p-channel transistor which the timing control signal is inputted;
- a first terminal of the second n-channel transistor which the inverted timing control signal is inputted;
- a second terminal of the second n-channel transistor, and a second terminal of the second p-channel transistor electrically connected to the second terminal of the second n-channel transistor;
- and
- wherein the second terminal of the second n-channel transistor and the second terminal of the second p-channel transistor are electrically connected to the input terminal of the inverter circuit.
9 more elements
A semiconductor circuit characterized by comprising:
- a first n-channel transistor, a first p-channel transistor, a second n-channel transistor, a second p-channel transistor, and an inverter circuit, comprising:
- wherein a gate terminal of the first n-channel transistor and a gate terminal of the first p-channel transistor to which a first input signal is inputted;
- a first terminal of the first p-channel transistor to which a timing control signal is inputted;
- a first terminal of the first n-channel transistor to which an inverted timing control signal is inputted;
- a second terminal of the first n-channel transistor, and a second terminal of the first p-channel transistor electrically connected to the second terminal of the first n-channel transistor;
- wherein the second terminal of the first n-channel transistor and the second terminal of the first p-channel transistor are electrically connected to an input terminal of the inverter circuit;
- a gate terminal of the second n-channel transistor and a gate terminal of the second p-channel transistor to which a second signal that is outputted from an output terminal of the inverter circuit is inputted;
- a first terminal of the second n-channel transistor to which the timing control signal is inputted;
- a first terminal of the second p-channel transistor to which the inverted timing control signal is inputted;
- wherein second terminals of the second n-channel transistor and the second p-channel transistor electrically connected to each other;
- and
- wherein the second terminals of the second n-channel transistor and the second p-channel transistor are electrically connected to the input terminal of the inverter circuit.
9 more elements
A semiconductor circuit characterized by comprising:
- a first n-channel transistor, a first p-channel transistor, a second n-channel transistor, a second p-channel transistor, a first inverter circuit, a third n-channel transistor, a third p-channel transistor, a fourth n-channel transistor, a fourth p-channel transistor, and a second inverter circuit, comprising:
- a gate terminal of the first n-channel transistor and a gate terminal of the first p-channel transistor to which a first input signal is inputted;
- a first terminal of the first n-channel transistor to which a clock signal is inputted;
- a first terminal of the first p-channel transistor to which an inverted clock signal is inputted;
- a second terminal of the first n-channel transistor, and a second terminal of the first p-channel transistor electrically connected to the second terminal of the first n-channel transistor;
- wherein the second terminal of the first n-channel transistor and the second terminal of the first p-channel transistor are electrically connected to an input terminal of the first inverter circuit;
- a gate terminal of the second n-channel transistor and a gate terminal of the second p-channel transistor to which a second signal that is outputted from an output terminal of the first inverter circuit is inputted;
- a first terminal of the second p-channel transistor to which the clock signal is inputted;
- a first terminal of the second n-channel transistor to which the inverted clock signal is inputted;
- a second terminal of the second n-channel transistor, and a second terminal of the second p-channel transistor electrically connected to the second terminal of the second n-channel transistor;
- wherein the second terminals of the second n-channel transistor and the second p-channel transistor are electrically connected to the input terminal of the first inverter circuit;
- a gate terminal of the third n-channel transistor and a gate terminal of the third p-channel transistor to which the second input signal is inputted;
- a first terminal of the third p-channel transistor to which the clock signal is inputted;
- a first terminal of the third n-channel transistor to which the inverted clock signal is inputted;
- a second terminal of the third n-channel transistor, the second terminal of the third n-channel transistor, and a second terminal of the third p-channel transistor;
- wherein the second terminal of the third n-channel transistor and the second terminal of the third p-channel transistor are electrically connected to an input terminal of the second inverter circuit;
- a gate terminal of the fourth n-channel transistor and a gate terminal of the fourth p-channel transistor to which a third signal that is outputted from an output terminal of the second inverter circuit is inputted;
- a first terminal of the fourth n-channel transistor to which the clock signal is inputted;
- a first terminal of the fourth p-channel transistor to which the inverted clock signal is inputted;
- a second terminal of the fourth n-channel transistor, and a second terminal of the fourth p-channel transistor electrically connected to the second terminal of the fourth n-channel transistor;
- and
- wherein the second terminals of the fourth n-channel transistor and the fourth p-channel transistor are electrically connected to the input terminal of the second inverter circuit.
19 more elements
A semiconductor circuit characterized by comprising:
- a first n-channel transistor, a first p-channel transistor, a second n-channel transistor, a second p-channel transistor, a first inverter circuit, a third n-channel transistor, a third p-channel transistor, a fourth n-channel transistor, a fourth p-channel transistor, and a second inverter circuit, comprising
- a gate terminal of the first n-channel transistor and a gate terminal of the first p-channel transistor to which a first input signal is inputted;
- a first terminal of the first p-channel transistor to which a clock signal is inputted;
- a first terminal of the first n-channel transistor to which an inverted clock signal is inputted;
- a second terminal of the first n-channel transistor, and a second terminal of the first p-channel transistor which is electrically connected to the second terminal of the first n-channel transistor;
- wherein the second terminals of the first n-channel transistor and the first p-channel transistor are electrically connected to an input terminal of the first inverter circuit;
- wherein a gate terminal of the second n-channel transistor and a gate terminal of the second p-channel transistor to which a second signal that is outputted from an output terminal of the first inverter circuit is inputted;
- a first terminal of the second n-channel transistor to which the clock signal is inputted;
- a first terminal of the second p-channel transistor to which the inverted clock signal is inputted;
- a second terminal of the second n-channel transistor, and a second terminal of the second p-channel transistor which is electrically connected to the second terminal of the second n-channel transistor;
- wherein the second terminal of the second n-channel transistor and the second terminal of the second p-channel transistor are electrically connected to the input terminal of the first inverter circuit;
- a gate terminal of the third n-channel transistor and a gate terminal of the third p-channel transistor to which the second input signal is inputted;
- a first terminal of the third n-channel transistor to which a clock signal is inputted;
- a first terminal of the third p-channel transistor to which an inverted clock signal is inputted;
- a second terminal of the third n-channel transistor, and a second terminal of the third p-channel transistor which is electrically connected to the second terminal of the third n-channel transistor;
- wherein the second terminals of the third n-channel transistor and the third p-channel transistor are electrically connected to an input terminal of the second inverter circuit;
- a gate terminal of the fourth n-channel transistor and a gate terminal of the fourth p-channel transistor to which a third signal that is outputted from an output terminal of the second inverter circuit is inputted;
- a first terminal of the fourth p-channel transistor to which the clock signal is inputted;
- a first terminal of the fourth n-channel transistor to which the inverted clock signal is inputted;
- a second terminal of the fourth n-channel transistor, and a second terminal of the fourth p-channel transistor which is electrically connected to the second terminal of the fourth n-channel transistor;
- and
- wherein the second terminals of the fourth n-channel transistor and the fourth p-channel transistor are electrically connected to the input terminal of the second inverter circuit.
19 more elements
A display device characterized by comprising:
- a gate driver, a source driver, and a pixel portion connected to the gate driver and the source driver,
- wherein the source driver includes a shift register circuit and a latch circuit;
- wherein the gate driver includes a shift register circuit;
- wherein each of the shift register circuit and the latch circuit of the source driver and the shift register circuit of the gate driver has a semiconductor circuit comprising a first n-channel transistor, a first p-channel transistor, a second n-channel transistor, a second p-channel transistor, and an inverter circuit;
- and
- wherein the semiconductor circuit comprises:
- a gate terminal of the first n-channel transistor and a gate terminal of the first p-channel transistor to which a first input signal is inputted;
- a first terminal of the first n-channel transistor to which a timing control signal is inputted;
- a first terminal of the first p-channel transistor to which an inverted timing control signal is inputted;
- a second terminal of the first n-channel transistor, and a second terminal of the first p-channel transistor which is electrically connected to the second terminal of the first n-channel transistor;
- wherein the second terminals of the first n-channel transistor and the first p-channel transistor are electrically connected to an input terminal of the inverter circuit;
- a gate terminal of the second n-channel transistor and a gate terminal of the second p-channel transistor to which a second signal that is outputted from an output terminal of the inverter circuit is inputted;
- a first terminal of the second p-channel transistor to which the timing control signal is inputted;
- a first terminal of the second n-channel transistor to which the inverted timing control signal is inputted;
- a second terminal of the second n-channel transistor, and a second terminal of the second p-channel transistor which is electrically connected to the second terminal of the second n-channel transistor;
- and
- wherein the second terminal of the second n-channel transistor and the second terminal of the second p-channel transistor are electrically connected to the input terminal of the inverter circuit.
14 more elements
A display device characterized by comprising:
- a gate driver, a source driver, and a pixel portion connected to the gate driver and the source driver,
- wherein the source driver includes a shift register circuit and a latch circuit;
- wherein the gate driver includes a shift register circuit;
- wherein each of the shift register circuit of the source driver and the shift register circuit of the gate driver has a semiconductor circuit having a first n-channel transistor, a first p-channel transistor, a second n-channel transistor, a second p-channel transistor, and an inverter circuit;
- and
- wherein the semiconductor circuit comprises:
- a gate terminal of the first n-channel transistor and a gate terminal of the first p-channel transistor to which a first input signal is inputted;
- a first terminal of the first p-channel transistor to which a timing control signal is inputted;
- a first terminal of the first n-channel transistor to which an inverted timing control signal is inputted;
- a second terminal of the first n-channel transistor, and a second terminal of the first p-channel transistor which is electrically connected to the second terminal of the first n-channel transistor;
- wherein the second terminal of the first n-channel transistor and the second terminal of the first p-channel transistor are electrically connected to an input terminal of the inverter circuit;
- a gate terminal of the second n-channel transistor and a gate terminal of the second p-channel transistor to which a second signal that is outputted from an output terminal of the inverter circuit is inputted;
- a first terminal of the second n-channel transistor to which the timing control signal is inputted;
- a first terminal of the second p-channel transistor to which the inverted timing control signal is inputted;
- a second terminal of the second n-channel transistor, and a second terminal of the second p-channel transistor which is electrically connected to the second terminal of the second n-channel transistor;
- and
- wherein the second terminal of the second n-channel transistor and the second terminal of the second p-channel transistor are electrically connected to the input terminal of the inverter circuit.
14 more elements
A display device characterized by comprising:
- a gate driver, a source driver, and a pixel portion connected to the gate driver and the source driver,
- wherein the source driver includes a shift register circuit and a latch circuit;
- wherein the gate driver includes a shift register circuit;
- wherein each of the shift register circuit of the source driver and the shift register circuit of the gate driver has multiple semiconductor circuits each having a first n-channel transistor, a first p-channel transistor, a second n-channel transistor, a second p-channel transistor, a first inverter circuit, a third n-channel transistor, a third p-channel transistor, a fourth n-channel transistor, a fourth p-channel transistor, and a second inverter circuit;
- and
- wherein each of the semiconductor circuits comprises:
- a gate terminal of the second n-channel transistor and a gate terminal of the second p-channel transistor to which a second signal that is outputted from an output terminal of the first inverter circuit is inputted;
- a first terminal of the second p-channel transistor to which the clock signal is inputted;
- a first terminal of the second n-channel transistor to which the inverted clock signal is inputted;
- a second terminal of the second n-channel transistor, and a second terminal of the second p-channel transistor electrically connected to the second terminal of the second n-channel transistor;
- wherein the second terminal of the second n-channel transistor and the second terminal of the second p-channel transistor are electrically connected to an input terminal of the first inverter circuit;
- a gate terminal of the third n-channel transistor and a gate terminal of the third p-channel transistor to which the second input signal is inputted;
- a first terminal of the third p-channel transistor to which a clock signal is inputted;
- a first terminal of the third n-channel transistor to which a inverted clock signal is inputted;
- a first terminal of the third n-channel transistor, and a second terminal of the third p-channel transistor which is electrically connected to the second terminal of the third n-channel transistor;
- wherein the second terminal of the third n-channel transistor and the second terminal of the third p-channel transistor are electrically connected to an input terminal of the second inverter circuit.
- a gate terminal of the fourth n-channel transistor and a gate terminal of the fourth p-channel transistor to which a third signal that is outputted from an output terminal of the second inverter circuit is inputted;
- a first terminal of the fourth n-channel transistor to which the clock signal is inputted;
- a first terminal of the fourth p-channel transistor to which the inverted clock signal is inputted;
- a second terminal of the fourth n-channel transistor, and a second terminal of the fourth p-channel transistor which is electrically connected to the second terminal of the fourth n-channel transistor;
- and
- wherein the second terminal of the fourth n-channel transistor and the second terminal of the fourth p-channel transistor are electrically connected to the input terminal of the second inverter circuit.
19 more elements
A display device characterized by comprising:
- a gate driver, a source driver, and a pixel portion connected to the gate driver and the source driver;
- wherein the source driver includes a shift register circuit and a latch circuit;
- wherein the gate driver includes a shift register circuit;
- wherein each of the shift register circuit of the source driver and the shift register circuit of the gate driver has multiple semiconductor circuits each having a first n-channel transistor, a first p-channel transistor, a second n-channel transistor, a second p-channel transistor, a first inverter circuit, a third n-channel transistor, a third p-channel transistor, a fourth n-channel transistor, a fourth p-channel transistor, and a second inverter circuit;
- and
- wherein each of the semiconductor circuits comprises:
- a gate terminal of the first n-channel transistor and a gate terminal of the first p-channel transistor to which a first input signal is inputted;
- a first terminal of the first p-channel transistor to which a clock signal is inputted;
- a first terminal of the first n-channel transistor to which an inverted clock signal is inputted;
- a second terminal of the first n-channel transistor, and a second terminal of the first p-channel transistor which is electrically connected to the second terminal of the first n-channel transistor;
- wherein the second terminal of the first n-channel transistor and the second terminal of the first p-channel transistor are electrically connected to an input terminal of the first inverter circuit;
- a gate terminal of the second n-channel transistor and a gate terminal of the second p-channel transistor to which a second signal that is outputted from an output terminal of the first inverter circuit is inputted;
- a first terminal of the second n-channel transistor to which the clock signal is inputted;
- a first terminal of the second p-channel transistor to which the inverted clock signal is inputted;
- a second terminal of the second n-channel transistor, and a second terminal of the second p-channel transistor which is electrically connected to the second terminal of the second n-channel transistor;
- and
- wherein the second terminal of the second n-channel transistor and the second terminal of the second p-channel transistor are electrically connected to the input terminal of the first inverter circuit;
- a gate terminal of the third n-channel transistor and a gate terminal of the third p-channel transistor to which the second input signal is inputted;
- a first terminal of the third n-channel transistor to which a clock signal is inputted;
- a first terminal of the third p-channel transistor to which the inverted clock signal is inputted;
- a second terminal of the third n-channel transistor, and a second terminal of the third p-channel transistor which is electrically connected to the second terminal of the third n-channel transistor;
- wherein the second terminal of the third n-channel transistor and the second terminal of the third p-channel transistor are electrically connected to an input terminal of the second inverter circuit;
- a gate terminal of the fourth n-channel transistor and a gate terminal of the fourth p-channel transistor to which a third signal that is outputted from an output terminal of the second inverter circuit is inputted;
- a first terminal of the fourth p-channel transistor to which the clock signal is inputted;
- a first terminal of the fourth n-channel transistor to which the inverted clock signal is inputted;
- a second terminal of the fourth n-channel transistor, and a second terminal of the fourth p-channel transistor which is electrically connected to the second terminal of the fourth n-channel transistor;
- and
- wherein the second terminal of the fourth n-channel transistor and the second terminal of the p-channel transistor are electrically connected to the input terminal of the second inverter circuit.
25 more elements
An electronic apparatus characterized by comprising a display panel including:
- a gate driver, a source driver, and a pixel portion connected to the gate driver and the source driver,
- wherein the source driver includes a shift register circuit and a latch circuit;
- wherein the gate driver includes a shift register circuit;
- wherein each of the shift register circuit and the latch circuit of the source driver and the shift register circuit of the gate driver has a semiconductor circuit having a first n-channel transistor, a first p-channel transistor, a second n-channel transistor, a second p-channel transistor, and an inverter circuit;
- and
- wherein the semiconductor circuit comprises:
- a gate terminal of the first n-channel transistor and a gate terminal of the first p-channel transistor to which a first input signal is inputted;
- a first terminal of the first n-channel transistor to which a timing control signal is inputted;
- a first terminal of the first p-channel transistor to which an inverted timing control signal is inputted;
- a second terminal of the first n-channel transistor, and a second terminal of the first p-channel transistor which is electrically connected to the second terminal of the first n-channel transistor;
- wherein the second terminal of the first n-channel transistor and the second terminal of the first p-channel transistor are electrically connected to an input terminal of the inverter circuit;
- a gate terminal of the second n-channel transistor and a gate terminal of the second p-channel transistor to which a second signal that is outputted from an output terminal of the inverter circuit is inputted;
- a first terminal of the second p-channel transistor to which the timing control signal is inputted;
- a first terminal of the second n-channel transistor to which the inverted timing control signal is inputted;
- a second terminal of the second n-channel transistor, and a second terminal of the second p-channel transistor which is electrically connected to the second terminal of the second n-channel transistor;
- and
- wherein the second terminal of the second n-channel transistor and the second terminal of the second p-channel transistor are electrically connected to the input terminal of the inverter circuit.
14 more elements
An electronic apparatus characterized by comprising a display panel including:
- a gate driver, a source driver, and a pixel portion connected to the gate driver and the source driver,
- wherein the source driver includes a shift register circuit and a latch circuit;
- wherein the gate driver includes a shift register circuit;
- wherein each of the shift register circuit of the source driver and the shift register circuit of the gate driver has a semiconductor circuit having a first n-channel transistor, a first p-channel transistor, a second n-channel transistor, a second p-channel transistor, and an inverter circuit;
- and
- wherein the semiconductor circuit comprises:
- a gate terminal of the first n-channel transistor and a gate terminal of the first p-channel transistor to which a first input signal is inputted;
- a first terminal of the first p-channel transistor to which a timing control signal is inputted;
- a first terminal of the first n-channel transistor to which an inverted timing control signal is inputted;
- a second terminal of the first n-channel transistor, and a second terminal of the first p-channel transistor which is electrically connected to the second terminal of the first n-channel transistor;
- wherein the second terminal of the first n-channel transistor and the second terminal of the first p-channel transistor are electrically connected to an input terminal of the inverter circuit;
- a gate terminal of the second n-channel transistor and a gate terminal of the second p-channel transistor to which a second signal that is outputted from an output terminal of the inverter circuit is inputted;
- a first terminal of the second n-channel transistor to which the timing control signal is inputted;
- a first terminal of the second p-channel transistor to which the inverted timing control signal is inputted;
- a second terminal of the second n-channel transistor, and a second terminal of the second p-channel transistor which is electrically connected to the second terminal of the second n-channel transistor;
- and
- wherein the second terminal of the second n-channel transistor and the second terminal of the second p-channel transistor are electrically connected to the input terminal of the inverter circuit.
14 more elements
An electronic apparatus characterized by comprising a display panel including:
- a gate driver, a source driver, and a pixel portion connected to the gate driver and the source driver,
- wherein the source driver includes a shift register circuit and a latch circuit;
- wherein the gate driver includes a shift register circuit;
- wherein each of the shift register circuit of the source driver and the shift register circuit included in the gate driver has multiple semiconductor circuits each having a first n-channel transistor, a first p-channel transistor, a second n-channel transistor, a second p-channel transistor, a first inverter circuit, a third n-channel transistor, a third p-channel transistor, a fourth n-channel transistor, a fourth n-channel transistor, and a second inverter circuit;
- and
- wherein each of the semiconductor circuits comprises:
- a gate terminal of the first n-channel transistor and a gate terminal of the first p-channel transistor to which a first input signal is inputted;
- a first terminal of the first n-channel transistor to which a clock signal is inputted;
- a first terminal of the first p-channel transistor to which an inverted clock signal is inputted;
- a second terminal of the first n-channel transistor, and a second terminal of the first p-channel transistor which is electrically connected to the second terminal of the first n-channel transistor;
- wherein the second terminal of the first n-channel transistor and the second terminal of the first p-channel transistor are electrically connected to an input terminal of the first inverter circuit;
- a gate terminal of the second n-channel transistor and a gate terminal of the second p-channel transistor to which a second signal that is outputted from an output terminal of the first inverter circuit is inputted;
- a first terminal of the second p-channel transistor to which the clock signal is inputted;
- a first terminal of the second n-channel transistor to which the inverted clock signal is inputted;
- a second terminal of the second n-channel transistor, and a second terminal of the second p-channel transistor which is electrically connected to the second terminal of the second n-channel transistor;
- wherein the second terminal of the second n-channel transistor and the second terminal of the second p-channel transistor are electrically connected to the input terminal of the first inverter circuit;
- a gate terminal of the third n-channel transistor and a gate terminal of the third p-channel transistor to which the second input signal is inputted;
- a first terminal of the third p-channel transistor to which a clock signal is inputted;
- a first terminal of the third n-channel transistor to which a inverted clock signal is inputted;
- a second terminal of the third n-channel transistor and a second terminal of the third p-channel transistor electrically connected to each other;
- wherein the second terminal of the third n-channel transistor and the second terminal of the third p-channel transistor are electrically connected to an input terminal of the second inverter circuit;
- a gate terminal of the fourth n-channel transistor and a gate terminal of the fourth p-channel transistor to which a third signal that is outputted from an output terminal of the second inverter circuit is inputted;
- a first terminal of the fourth n-channel transistor to which the clock signal is inputted;
- a first terminal of the fourth p-channel transistor to which the inverted clock signal is inputted;
- a second terminal of the fourth n-channel transistor, and a second terminal of the fourth p-channel transistor which is electrically connected to the second terminal of the fourth n-channel transistor;
- and
- wherein the second terminal of the fourth n-channel transistor and the second terminal of the fourth p-channel transistor are electrically connected to the input terminal of the second inverter circuit.
24 more elements
An electronic apparatus characterized by comprising a display panel including:
- a gate driver, a source driver, and a pixel portion connected to the gate driver and the source driver,
- wherein the source driver includes a shift register circuit and a latch circuit;
- wherein the gate driver includes a shift register circuit;
- wherein each of the shift register circuit of the source driver and the shift register circuit of the gate driver has multiple semiconductor circuits each having a first n-channel transistor, a first p-channel transistor, a second n-channel transistor, a second p-channel transistor, a first inverter circuit, a third n-channel transistor, a third p-channel transistor, a fourth n-channel transistor, a fourth n-channel transistor, and a second inverter circuit;
- and
- wherein each of the semiconductor circuits comprises:
- a gate terminal of the first n-channel transistor and a gate terminal of the first p-channel transistor to which a first input signal is inputted;
- a first terminal of the first p-channel transistor to which a clock signal is inputted;
- a first terminal of the first n-channel transistor to which an inverted clock signal is inputted;
- a second terminal of the first n-channel transistor, and a second terminal of the first p-channel transistor which is electrically connected to the second terminal of the first n-channel transistor;
- wherein the second terminals of the first n-channel transistor and the first p-channel transistor are electrically connected to an input terminal of the first inverter circuit;
- a gate terminal of the second n-channel transistor and a gate terminal of the second p-channel transistor to which a second signal that is outputted from an output terminal of the first inverter circuit is inputted;
- a first terminal of the second n-channel transistor to which the clock signal is inputted;
- a first terminal of the second p-channel transistor to which the inverted clock signal is inputted;
- a second terminal of the second n-channel transistor, and a second terminal of the second p-channel transistor which is electrically connected to the second terminal of the second n-channel transistor;
- wherein the second terminal of the second n-channel transistor and the second terminal of the second p-channel transistor are electrically connected to the input terminal of the first inverter circuit;
- a gate terminal of the third n-channel transistor and a gate terminal of the third p-channel transistor to which the second input signal is inputted;
- a first terminal of the third n-channel transistor to which a clock signal is inputted;
- a first terminal of the third p-channel transistor to which a inverted clock signal is inputted;
- a second terminal of the third n-channel transistor, and a second terminal of the third p-channel transistor electrically connected to the second terminal of the third n-channel transistor;
- wherein the second terminal of the third n-channel transistor and the second terminal of the third p-channel transistor are electrically connected to an input terminal of the second inverter circuit;
- a gate terminal of the fourth n-channel transistor and a gate terminal of the fourth p-channel transistor to which a third signal that is outputted from an output terminal of the second inverter circuit is inputted;
- a first terminal of the fourth p-channel transistor to which the clock signal is inputted;
- a first terminal of the fourth n-channel transistor to which the inverted clock signal is inputted;
- a second terminal of the fourth n-channel transistor, and a second terminal of the fourth p-channel transistor which is electrically connected to the second terminal of the fourth n-channel transistor;
- and
- wherein the second terminal of the fourth n-channel transistor and the second terminal of the fourth p-channel transistor are electrically connected to the input terminal of the second inverter circuit.
24 more elements
Dependencies are inferred from the claim text.