Timing recovery circuit with multiple stages

A timing recovery circuit, comprising:

• a first oscillating circuit configured to produce a first timing signal at an output node;
• a second oscillating circuit configured to produce a second timing signal at an output node;
• a first decimation circuit coupled to a supply node of a first clock signal and to the output node of said first oscillating circuit to produce at an output node a second clock signal made by decimating pulses of the first clock signal in response to the first timing signal;
• and
• a second decimation circuit coupled to the output node of said first decimation circuit and to the output node of said second oscillating circuit to produce a third clock signal made by decimating pulses of the second clock signal in response to the second timing signal,
• wherein one of the first timing signal and the second timing signal has a fixed cycle, and another one of the first timing signal and the second timing signal has a cycle responsive to feedback control.