Decoder circuit

Abstract

A decoder circuit, for example a dual-rail decoder, receives input signals (43) from the end of a communications bus (not shown). The parity is calculated over the data wires (Do, D1, D2, D3) using exclusive OR gates (45, 47, and 49). The calculated data parity signal (51) is compared with a transmitted parity signal (53) (shown as “carry”) in an exclusive OR gate (55). Rather than connecting the control signal (57) from the exclusive OR gate (55) directly to the multiplexers (590, 591, 592, 593), the control signal (57) is instead connected to a gating circuit (71). The gating circuit (71), for example a AND gate, receives the control signal (57) as a first input signal. The gating circuit (71) also receives a second input signal in the form of a gating control signal (73). The gating control signal (73) is delayed by a predetermined amount, for example corresponding to the worst case delay of the signals in the input data signals (43). Thus, the gating control signal (73) does not control the gating circuit until such time as all of the data signals are valid, ie until the last transition on the data signal (43) has occurred, thereby preventing glitches and reducing power consumption in the decoder circuit.

Dependencies are inferred from the claim text.