Phase-locked loop with a digital calibration loop and an analog calibration loop
AssigneeTexas Instruments Incorporated
InventorsJames Brown, Hans Cramer
Life of this patent
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Abstract
A phase-locked loop (PLL) architecture (100) is provided that includes a voltage-controlled oscillator (VCO) (116). The PLL architecture (100) also includes a digital calibration loop (132) coupled to the VCO (116). The digital calibration loop (132) implements a digital filter (126) to provide a digital control to the VCO (116) for centering a VCO frequency output. The PLL architecture (100) also includes an analog calibration loop (130) coupled to the VCO (116). The analog calibration loop (130) provides an analog control to the VCO (116) for adjusting the centered VCO frequency output.
Claims20
A phase-locked loop (PLL) architecture, comprising:
- a voltage-controlled oscillator (VCO);
- a digital calibration loop coupled to the VCO, the digital calibration loop implements a digital filter to provide a digital control to the VCO for centering a VCO frequency output;
- and
- an analog calibration loop coupled to the VCO, the analog calibration loop provides an analog control to the VCO for adjusting the centered VCO frequency output.
A method for implementing a phase-locked loop (PLL), comprising:
- providing a first voltage controlled oscillator (VCO) calibration based on a digital filter output;
- and
- providing a second VCO calibration based on an analog loopfilter output,
- wherein the second VCO calibration adjusts a VCO frequency within a step size of the first VCO calibration.
Dependencies are inferred from the claim text.