Clock signal input/output device for correcting clock signals

A clock signal correction method, comprising:

• dividing the frequency of a clock signal so that a signal with a lower frequency vis-à-vis the frequency of the clock signal is obtained;
• integrating the signal with the lower frequency so that an integration signal is obtained;
• comparing the signal with the lower frequency with a signal that is inverse thereto;
• and
• comparing the integration signal with a signal that is inverse thereto.

A clock signal input/output device, comprising:

• a frequency divider to be sent and receive a clock signal;
• a signal integrator to be sent or receive a signal output by the frequency divider;
• a first signal comparison circuit to be sent or receive a signal output by the signal integrator;
• a second signal comparison circuit to be sent or receive the signal output by the frequency divider;
• and
• a signal output circuit for outputting a clock output signal as a function of a signal output by the first signal comparison circuit, and a signal output by the second signal comparison circuit, wherein a signal edge of the clock output signal extending in a first direction is triggered by a signal edge of the signal output by the second signal comparison circuit, and a second signal edge of the clock output signal extending in a second direction opposite to the first direction is triggered by a signal edge of the signal output by the first signal comparison circuit.

A clock signal correction method, comprising:

• dividing the frequency of a clock signal so that a signal with a lower frequency vis-à-vis the frequency of the clock signal is obtained;
• integrating the signal with the lower frequency, so that an integration signal is obtained;
• comparing the signal with the lower frequency with a signal that is inverse thereto, so that a first comparison signal is obtained;
• comparing the integration signal with a signal that is inverse thereto, so that a second comparison signal is obtained;
• and
• outputting a clock output signal, wherein a signal edge of the clock output signal extending in a first direction is triggered by a signal edge of the first comparison signal, and a signal edge of the clock output signal extending in a second direction opposite to the first direction is triggered by a signal edge of the second comparison signal.