Digital pulse width modulator
AssigneePowervation Limited
InventorsEamon O'Malley, Karl Rinne
Life of this patent
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Abstract
A DPWM (1) has a delay lock loop (4) which receives an input clock signal and provides an out-of-phase delayed clock at the output of each of eight delay cells (35). A multiplexer (5) selects one of the delay cell outputs at any one time. This allows the DPWM (1) to have eight times the resolution which would otherwise be achieved with the same input clock. A programmable module (2) has a control block (20) which interfaces with external CPU and DSP hosts and transmits programmed parameters to finite state machine controllers (15), each providing an independent output.
Claims26
1-29. (canceled)
A DPWM comprising a counter and a comparator, characterised in that the DPWM further comprises a delay circuit for delaying a received clock signal to provide multiple clock phases to simulate a higher frequency clock,
- wherein the delay circuit comprises a delay-locked loop circuit having a plurality of delay cells each providing a clock phase transition within the received clock period,
- wherein said module comprises a control block for interfacing with an external host, and a plurality of controllers for providing outputs, and
- wherein the controllers are state machines.
Dependencies are inferred from the claim text.