Delay-lock loop and method having high resolution and wide dynamic range

Abstract

A delay-lock loop includes a phase detector comparing the phase of a digital input signal to the phase of a feedback signal. The phase detector generates a corresponding control signal that is used to control the delay of a delay line. A multiplexer couples the input signal to the input of the delay line and thereafter couples a signal received from the output of the delay line to the input of the delay line so that the delay line functions as several individual delay lines. At least one digital signal that has propagated through the delay line is used as a feedback signal that is coupled from the output of the delay line to the phase detector by a signal router. The phase of the signal coupled to the phase detector by the router is therefore locked to the phase of the input signal.

Dependencies are inferred from the claim text.