Phase locked system for generating distributed clocks

A phase locked loop (PLL) system, wherein the PLL system receives a first clock signal and provides a second clock signal synchronized with the first clock signal when the PLL system is locked, wherein the second clock signal has a gear relationship with the first clock signal, comprising:

• a pre-divider coupled to the first clock signal to generate a third clock signal;
• a loop-divider coupled to the second clock signal to generate a fourth clock signal, wherein the frequencies of the third and fourth clock signals are substantially equal when the PLL system is locked;
• a phase comparator making a comparison between the third and fourth clock signals;
• a charge pump circuit producing a control voltage based on the output of the phase comparator;,
• a voltage-controlled oscillator to generate the second clock signal based on the control voltage;
• and
• a detection terminal connected with the third or fourth clock signal to be accessed for the detection of the synchronizing edges of the first and second clock signals.

A phase locked loop (PLL) system, comprising:

• a PLL apparatus receiving a first clock signal of frequency f1 to provide a second clock signal of frequency f2 synchronized with the first clock signal when the PLL system is locked, wherein the second clock signal has a gear relationship with the first clock signal;
• at least one additional divider coupled to the first and/or second clock signals to generate a sample clock signal the frequency of which is a common divisor of the first and second clock signals;
• and
• a synchronizing-edge detector to generate an output clock signal indicative of the synchronizing edges of the first and second clock signals by detecting the edges of the sample clock signal.