Analog buffer circuit
AssigneeNEC Corporation
InventorYoshitaka Matsuoka
Life of this patent
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Abstract
An analog buffer circuit (10) includes a first p channel field effect transistor (11), an n channel field effect transistor (12) and a second p channel field effect transistor (13). The transistors are connected to one another in serial between power supplying terminals (VDD and GND). The transistors have gates connected to an input terminal (IN) in common. An output terminal (OUT) is connected to a connecting point between the n channel transistor and the second p channel transistor. With this structure, output voltage which appears on the output terminal is approximately proportional to input voltage supplied to the input terminal.
Claims8
An analog buffer having an approximately a linear input output voltage characteristic, said analog buffer comprising:
- three field effect transistors disposed between an input terminal and an output terminal for accomplishing the approximately linear input output voltage characteristic.
Dependencies are inferred from the claim text.