Clock generator
AssigneeCSEM Centre Suisse d'Electronique et de Microtechique SA, Recherche et Developpement
InventorDavid Ruffieux
Life of this patent
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Abstract
This clock generator comprises an oscillator for generating an alternating current pilot signal and a pulse formatting circuit which is intended to convert the pilot signal from the oscillator into a pulse clock signal having a duty factor of at least approximately 50%. According to one implementation, a series of at least two inverters is provided, the input of the first inverter being controlled by the alternating current pilot signal and the output of the second inverter supplying the clock signal. A power supply means may also be provided to supply the inverters with a regulated power supply voltage dependent on the signals appearing at the outputs of the inverters.
Claims13
A clock generator comprising an oscillator for generating an alternating current pilot signal (in_ana) and a pulse formatting circuit which is intended to convert said current pilot signal from said oscillator into a pulse clock signal (out_r2r ) having a duty factor of approximately 50%, said clock generator further comprising:
- a series of at least a first and a second inverters, said first inverter having an input controlled by said alternating current pilot signal (in_ana) and said second inverter having an output supplying said clock signal (out_r2r ), and
- power supply means for supplying said inverters with a regulated power supply voltage (V_reg) according to signals appearing at an output of said first inverter and at said output of said second inverter.
Dependencies are inferred from the claim text.