Phase-locked loop and method thereof and a phase-frequency detector and method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorYoung-Kyun Cho
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AssigneeSamsung Electronics Co., Ltd.
InventorYoung-Kyun Cho
Estimating the term…
The phase-frequency detector may include a first flip-flop configured to generate a first signal, the first signal transitioning to a first logic level in response to a first edge of a first input signal and transitioning to a second logic level in response to a delayed reset signal and a second flip-flop configured to generate a second signal, the second signal transitioning to the first logic level in response to a second edge of a second input signal and transitioning to the second logic level in response to the delayed reset signal. The phase-frequency detector may further include a first delay unit configured to delay a reset signal to generate the delayed reset signal and a second delay unit configured to delay the reset signal to generate an output control signal for adjusting at least one of the first and second signals.
A phase-frequency detector, comprising:
A phase-locked loop, comprising:
A method of phase frequency detection, comprising:
A method of phase detection, comprising:
Dependencies are inferred from the claim text.