Output buffer and method having a supply voltage insensitive slew rate

An output buffer comprising:

• a first voltage-controlled switch having a first terminal coupled to a first power supply voltage, a second terminal coupled to an output terminal, and a control terminal coupled to receive a first digital signal, the first voltage-controlled switch being closed responsive to a first value of the first digital signal and being opened responsive to a second value of the first digital signal, the rate at which the voltage at the output terminal transitions to the first power supply voltage when the first voltage-controlled switch is closed responsive to receiving the first value of the first digital signal varying as a function of the magnitude of the first power supply voltage;
• and
• a second voltage-controlled switch having a first terminal coupled to a second power supply voltage, a second terminal coupled to the output terminal, and a control terminal coupled to receive a second digital signal, the second voltage-controlled switch being closed responsive to a second value of the second digital signal and being opened responsive to a first value of the second digital signal, the rate at which the voltage at the output terminal transitions to the second power supply voltage when the second voltage-controlled switch is closed responsive to receiving the second value of the second digital signal varying as a function of the magnitude of one of the first and second power supply voltages;
• a bias circuit coupled to the output terminal, the bias circuit being operable to bias the output terminal to a bias voltage that is intermediate the first and second power supply voltages;
• a first pre-driver receiving at least one of the first and second power supply voltages and generating the first digital signal responsive to a first data input signal, the pre-driver being operable to delay a transition of the first digital signal to the first value of the first digital signal as a function of the magnitude of at least one of the first and second supply voltages;
• and
• a second pre-driver receiving at least one of the first and second power supply voltages and generating the second digital signal responsive to a second data input signal, the pre-driver being operable to delay a transition of the second digital signal to the second value of the second digital signal as a function of the magnitude of at least one of the first and second supply voltages.

A memory device, comprising:

• a command decoder receiving memory command signals through externally accessible terminals, the command decoder generating memory control signals responsive to predetermined combinations of the command signals;
• an address decoder receiving address signals through externally accessible terminals, the address decoder generating row and column addressing signals responsive to the address signals;
• an array of memory cells arranged in rows and columns from which data are read and to which data are written at locations corresponding the address signals responsive to the memory control signals;
• and
• a data path extending between a plurality of externally accessible data bus terminals and the array of memory cells for coupling data signals to and from the memory arrays through externally accessible terminals, the data path including a data input buffer having input terminals coupled to the data bus terminals and output terminals coupled to the array of memory cells, and a data output buffer having input terminals coupled to the array of memory cells and output terminals coupled to the data bus terminals, the data output buffer comprising:
• a final driver powered by a power supply voltage, the final driver being operable to generate a first value of a data output signal responsive to receiving a first digital signal and to generate a second value of the data output signal responsive to receiving a second digital signal, the rate at which the final driver transitions the data output signal to at least one of the first and second values responsive to the digital signals varying with the magnitude of the power supply voltage;
• and
• a pre-driver receiving the power supply voltage and generating the first and second digital signals responsive to a data input signal, the pre-driver being operable to delay the first digital signal relative to the second digital signal, the magnitude of the delay being a function of the magnitude of the supply voltage and being adjusted to allow the pre-driver to compensate for the variations in the rate at which the final driver transitions the data output signal responsive to variations in the magnitude of the power supply voltage.

A memory device, comprising:

• a command decoder receiving memory command signals through externally accessible terminals, the command decoder generating memory control signals responsive to predetermined combinations of the command signals;
• an address decoder receiving address signals through externally accessible terminals, the address decoder generating row and column addressing signals responsive to the address signals;
• an array of memory cells arranged in rows and columns from which data are read and to which data are written at locations corresponding the address signals responsive to the memory control signals;
• and
• a data path extending between a plurality of externally accessible data bus terminals and the array of memory cells for coupling data signals to and from the memory arrays through externally accessible terminals, the data path including a data input buffer having input terminals coupled to the data bus terminals and output terminals coupled to the array of memory cells, and a data output buffer having input terminals coupled to the array of memory cells and output terminals coupled to the data bus terminals, the data output buffer comprising:
• a first voltage-controlled switch having a first terminal coupled to a first power supply voltage, a second terminal coupled to an output terminal, and a control terminal coupled to receive a first digital signal, the first voltage-controlled switch being closed responsive to a first value of the first digital signal and being opened responsive to a second value of the first digital signal, the rate at which the voltage at the output terminal transitions to the first power supply voltage when the first voltage-controlled switch is closed responsive to receiving the first value of the first digital signal varying as a function of the magnitude of the first power supply voltage;
• a second voltage-controlled switch having a first terminal coupled to a second power supply voltage, a second terminal coupled to the output terminal, and a control terminal coupled to receive a second digital signal, the second voltage-controlled switch being closed responsive to a second value of the second digital signal and being opened responsive to a first value of the second digital signal, the rate at which the voltage at the output terminal transitions to the second power supply voltage when the second voltage-controlled switch is closed responsive to receiving the second value of the second digital signal varying as a function of the magnitude of one of the first and second power supply voltages;
• a bias circuit coupled to the output terminal, the bias circuit being operable to bias the output terminal to a bias voltage that is intermediate the first and second power supply voltages;
• a first pre-driver receiving at least one of the first and second power supply voltages and generating the first digital signal responsive to a first data input signal, the pre-driver being operable to delay a transition of the first digital signal to the first value of the first digital signal as a function of the magnitude of at least one of the first and second supply voltages;
• and
• a second pre-driver receiving at least one of the first and second power supply voltages and generating the second digital signal responsive to a second data input signal, the pre-driver being operable to delay a transition of the second digital signal to the second value of the second digital signal as a function of the magnitude of at least one of the first and second supply voltages.

A computer system, comprising:

• an integrated circuit processor having a plurality of externally accessible terminals coupled to a processor bus;
• an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
• and
• a dynamic random access memory coupled to a processor bus, the dynamic random access memory comprising:
• a command decoder receiving memory command signals through externally accessible terminals, the command decoder generating memory control signals responsive to predetermined combinations of the command signals;
• an address decoder receiving address signals through externally accessible terminals, the address decoder generating row and column addressing signals responsive to the address signals;
• an array of dynamic random access memory cells arranged in rows and columns from which data are read and to which data are written at locations corresponding the address signals responsive to the memory control signals;
• and
• a data path extending between a plurality of externally accessible data bus terminals and the array of memory cells for coupling data signals to and from the memory arrays through externally accessible terminals, the data path including a data input buffer having input terminals coupled to the data bus terminals and output terminals coupled to the array of memory cells, and a data output buffer having input terminals coupled to the array of memory cells and output terminals coupled to the data bus terminals, the data output buffer comprising:
• a final driver powered by a power supply voltage, the final driver being operable to generate a first value of a data output signal responsive to receiving a first digital signal and to generate a second value of the data output signal responsive to receiving a second digital signal, the rate at which the final driver transitions the data output signal to at least one of the first and second values responsive to the digital signals varying with the magnitude of the power supply voltage;
• and
• a pre-driver receiving the power supply voltage and generating the first and second digital signals responsive to a data input signal, the pre-driver being operable to delay the first digital signal relative to the second digital signal, the magnitude of the delay being a function of the magnitude of the supply voltage and being adjusted to allow the pre-driver to compensate for the variations in the rate at which the final driver transitions the data output signal responsive to variations in the magnitude of the power supply voltage.

In an output buffer generating an output signal at an output terminal, the output buffer having a first switch that closes to couple the output terminal to a first level and a second switch that closes to couple the output terminal to a second level that is different from the first level, the output terminal being biased to a third level that is intermediate the first and second levels, the rate at which the output signal generated at the output terminal transitions to at least one of the levels being a function of a power supply voltage, a method of maintaining the slew rate of the output signal in transitioning to at least one of the levels substantially constant as the magnitude of a supply voltage for the output buffer changes, the method comprising:

• closing the first switch after a first delay from opening the second switch to transition the output signal to the first level;
• closing the second switch after a first delay from opening the first switch to transition the output signal to the second level;
• and
• adjusting at least one of the first and second delays to compensate for a variation in the magnitude of the supply voltage so that the transition to at least one of the levels is substantially insensitive to variations in the magnitude of the power supply voltage.