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US 2006/0214686 A1Published application
Level shifting circuit and display element driving circuit using same
AssigneeSharp Kabushiki Kaisha
InventorTomoaki Nakao
Life of this patent
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Abstract
A P-channel MOS transistor and an N-channel MOS transistor are respectively controlled by a first control signal and a second control signal. The first control signal CTL1 and the second control signal CTL2 are independent from each other. The second control signal CTL2 is generated by a NOR circuit 2 to which a data signal DATA and a third control signal CTL3 are inputted. A load capacitor C1 which samples the first electric potential or the GND electric potential is configured by a gate capacitance of another MOS transistor.
Claims8
A level shifting circuit including:
- (A) a first MOS transistor of a P-channel type, whose source is connected to a power supply of a first electric potential which is higher than a GND electric potential;
- and (B) a second MOS transistor of an N-channel type, whose source is connected to a GND, and whose drain is connected to a drain of the first MOS transistor, the level shifting circuit performing a level shifting process with respect to an input signal, by (a) inputting, to a gate of the second MOS transistor, a gate signal which corresponds to the input signal to be subjected to the level shifting process, and (b) charging a load capacitor up to the first electric potential, or discharging the load capacitor down to the GND level, the load capacitor being connected to a connection point of respective drains of the first and the second MOS transistors,
- wherein:
- the first MOS transistor receives the first control signal inputted to the gate thereof as a gate signal, the first control signal being a binary signal which takes, as binary values, (i) the first electric potential and (ii) a second electric potential which is lower than the first electric potential;
- the first MOS transistor charges the load capacitor up to the first electric potential, when the first MOS transistor receives the first control signal of the second electric potential;
- the second MOS transistor receives a second control signal inputted to a gate thereof as a gate signal, the second control signal being a binary signal which takes, as binary values, (i) the GND electric potential and (ii) a third electric potential which is higher than the GND electric potential, the second control signal being independent from the first control signal;
- and
- the second MOS transistor discharges the load capacitor down to the GND electric potential when the second MOS transistor receives the second control signal of the third electric potential.
5 more elements
Dependencies are inferred from the claim text.