Back to results
US 2006/0214684 A1Published application
Interface circuit
AssigneeOki Electric Industry Co., Ltd.
InventorsKazuhiko Bando, Masanori Inazumi
Life of this patent
Estimating the term…
Abstract
As a data bus control enable signal is set to “H,” a PMOS turns on when a bi-directional bus is not in use (i.e., when a data bus active signal is “L”), so that the bi-directional bus is pulled down through a pull-down resistor. When the data bus control enable signal is set to “L,” the PMOS turns off, thus holding the bi-directional bus in a high-impedance state. By setting the data bus control enable signal in accordance with the specifications of a peripheral device connected thereto, the state of the bi-directional bus can be arbitrarily set when it is inactive.
Claims15
An interface circuit comprising:
- a three-state buffer for outputting, to a bi-directional bus, output data applied to an input thereof when an output enable signal is in an active state, and bringing an output thereof into a high-impedance state when the output enable signal is in an inactive state;
- a buffer for fetching a signal on said bi-directional bus as input data;
- a resistor connected between said bi-directional bus and a ground potential or a power supply potential through a switch unit;
- and
- a logical gate for bringing said switch unit into an on-state when said bi-directional bus is enabled by a bus control signal which is set in accordance with an output state of a device connected to said bi-directional bus and a bus access signal indicates that said bi-directional bus is not in use, and for bringing said switch unit into an off-state when said bi-directional bus is not enabled by the bus control signal or when the bus access signal indicates that said bi-directional bus is in use.
2 more elements
An interface circuit comprising:
- a three-state buffer for outputting output data applied to an input thereof to a bi-directional bus when a control signal is at a first level, and bringing an output thereof into a high-impedance state when the control signal is at a second level;
- a buffer for fetching a signal on said bi-directional bus as input data;
- and
- a logical gate for outputting the control signal at the first level when an output enable signal is in an active state or when said bi-directional bus is enabled by a bus control signal which is set in accordance with an output state of a device connected to said bi-directional bus and a bus access signal indicates that said bi-directional bus is not in use, and outputting the control signal at the second level when the output enable signal is in an inactive state and said bi-directional bus is not enabled by the bus control signal or when the output enable signal is in an inactive state and the bus access signal indicates that said bi-directional bus is in use.
1 more element
An interface circuit comprising:
- a three-state buffer for outputting output data applied to an input thereof to a bi-directional bus when an output enable signal is in an active state, and bringing an output thereof into a high-impedance state when the output enable signal is in an inactive state;
- a buffer for fetching a signal on said bi-directional bus as input data;
- a first resistor connected between said bi-directional bus and a ground potential through a first switch unit;
- a second resistor connected between said bi-directional bus and a power supply potential through a second switch unit;
- a first logical gate for bringing said first switch unit into an on-state when said bi-directional bus is enabled by a first bus control signal which is set in accordance with an output state of a separate device connected to said bi-directional bus and a bus access signal indicates that said bi-directional bus is not in use, and bringing said first switch unit into an off-state when said bi-directional bus is not enabled by the first bus control signal or when the bus access signal indicates that said bi-directional bus is in use;
- and
- a second logical gate for bringing said second switch unit into an on-state when said bi-directional bus is enabled by a second bus control signal which is set in accordance with an output state of the separate device and the bus access signal indicates that said bi-directional bus is not in use, and bringing said second switch unit into an off-state when said bi-directional bus is not enabled by the second bus control signal or when the bus access signal indicates that said bi-directional bus is in use.
4 more elements
Dependencies are inferred from the claim text.