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AssigneeCalifornia Institute of Technology
InventorAndre DeHon
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An apparatus and methods for interconnecting a plurality of nanoscale programmable logic array (PLA) clusters are disclosed. The appartus allows PLA clusters to be built at nanoscale dimensions, signal restoration to occur at the nanoscale, and interconnection between PLA clusters to be performed with nanoscale wiring. The nanoscale PLA, restoration, and interconnect arrangements can be constructed without using lithographic patterning to produce the nanoscale feature sizes and wire pitches. The nanoscale interconnection of the plurality of nanoscale PLA clusters can implement any logic function or any finite state machine. The nanoscale interconnect allows Manhattan (X,Y grid) routing between arbitrary nanoscale PLA clusters. The methods teach how to interconnect nanoscale PLAs with nanoscale interconnect and how to build arbitrary logic with nanoscale feature sizes without using lithography to pattern the nanoscale features.
An array of programmable logic array (PLA) clusters each cluster comprising:
A method of interconnecting a plurality of programmable logic array (PLA) clusters, the method comprising:
An array of programmable logic array (PLA) nanoscale clusters wherein an output of at least one PLA cluster forms an input of at least one other PLA cluster.
An array of interconnected programmable logic array (PLA) nanoscale clusters comprising nanoscale wires adapted to perform logical functions of the individual PLA nanoscale clusters and adapted to propagate signals throughout the array.
A method of implementing arbitrary logic at nanoscale, the method comprising:
A method for building a PLA cluster comprising:
Dependencies are inferred from the claim text.