Impedance adjustment circuit and integrated circuit device
AssigneeNEC Corporation
InventorTakashi Oguri
Life of this patent
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Abstract
An NMOS impedance adjustment circuit has a comparator circuit for comparing with a reference electric potential VREFn a divided voltage potential Vin produced by an NMOS array and an external reference resistance. The NMOS array simulates the impedance of an output buffer circuit on the basis of the comparison result. The comparator circuit has three differential circuits. Three 2-input NAND gates and a single three-input NAND gate take the majority of output values of the differential circuits and output the result from the comparator circuit. A reduction of impedance adjustment precision caused by variability within the chip can thereby be inhibited.
Claims8
An impedance adjustment circuit for simulating the buffer circuit of an integrated circuit device, comparing with a reference electric potential an electric potential that corresponds to the simulation result, and adjusting the impedance of said buffer circuit on the basis of the comparison result,
- whereby said comparison is carried out by three or more differential circuits, and said comparison result is obtained by selecting the majority from among the individual comparison results that are produced by the differential circuits.
An integrated circuit device comprising:
- a buffer circuit;
- an impedance adjustment circuit for simulating the buffer circuit, comparing with a reference electric potential a electric potential that corresponds to the simulation result, and adjusting the impedance of said buffer circuit on the basis of the comparison result;
- said impedance adjustment circuit carrying out said comparison by using three or more differential circuits;
- and
- said comparison result being obtained by selecting the majority from among the individual comparison results that are produced by the differential circuits.
Dependencies are inferred from the claim text.