Wafer level chip scale package having a gap and method for manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsMyeong-Soon Park, Hyun-Soo Chung, In-Young Lee, Jae-Sik Chung, Sung-Min Sim, Dong-Hyeon Jang, Young-Hee Song, Seung-Kwan Ryu
Life of this patent
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Abstract
A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.
Claims20
A package comprising:
- a semiconductor chip having a surface supporting an electrode pad;
- a first insulating layer provided on the surface of the semiconductor chip, the electrode pad being exposed through the first insulating layer;
- a seed metal layer provided on the electrode pad and the first insulating layer;
- a redistribution line provided on the seed metal layer and electrically connected to the electrode pad, the redistribution line having a bump land;
- a second insulating layer provided on the redistribution line so that a gap is provided between a portion of the second insulating layer and the bump land;
- and
- a solder bump provided on the bump land and electrically connected to the redistribution line, the solder bump surrounding a periphery of the portion of the second insulating layer.
A method for manufacturing a package, the package comprising a semiconductor chip having an electrode pad, the method comprising:
- forming a first insulating layer on a surface of the semiconductor chip so that the electrode pad is exposed through the first insulating layer;
- forming a seed metal layer on the electrode pad and the first insulating layer;
- forming a redistribution line on the seed metal layer, the redistribution line having a bump land, the redistribution line having a first opening through which a portion of the seed metal layer is exposed;
- removing the exposed portion of the seed metal layer;
- forming a second insulating layer on the redistribution line so that a gap is provided between a portion of the second insulating layer and the bump land;
- and
- forming a solder bump on the bump land to cover a periphery of the portion of the second insulating layer.
A package comprising:
- a semiconductor chip;
- a conductor provided on and electrically connected to the semiconductor chip, the conductor having a bump land;
- an insulating layer provided on the conductor so that a gap is provided between a portion of the insulating layer and the bump land;
- and
- a solder bump provided on the bump land, the solder bump surrounding a periphery of the portion of the insulating layer.
A method comprising:
- providing a semiconductor chip;
- providing a conductor on and electrically connected to the semiconductor chip, the conductor having a bump land;
- providing an insulating layer on the conductor so that a gap is provided between a portion of the insulating layer and the bump land;
- and
- providing a solder bump on the bump land, the solder bump surrounding a periphery of the portion of the insulating layer.
Dependencies are inferred from the claim text.