Multi-gate enhancement mode RF switch and bias arrangement

An RF switch, comprising:

• first and second control inputs;
• first, second and third DC blocking capacitors each having first and second terminals;
• first, second and third RF I/O ports, coupled respectively to the first terminals of the first, second and third DC blocking capacitors;
• a first enhancement mode multi-gate FET device having source, drain and gate terminals, wherein its source terminal is coupled to the second terminal of the first DC blocking capacitor, its drain terminal is coupled to the second terminal of the second DC blocking capacitor and its gate terminals are coupled to the first control input;
• a second enhancement mode multi-gate FET device having source, drain and gate terminals, wherein its source terminal is coupled to the second terminal of the first DC blocking capacitor, its drain terminal is coupled to the second terminal of the third DC blocking capacitor and its gate terminals are coupled to the second control input;
• and
• first and second bias resistances Rb, Rb′, each having first and second terminals, wherein the first bias resistor Rb has its first terminal coupled to the second terminal of the first DC blocking capacitor and its second terminal coupled to the first control input, and the second bias resistor Rb′ has its first terminal coupled to the second terminal of the first DC blocking capacitor and its second terminal coupled to the second control input.

A multi-mode RF switch, comprising:

• at least two independent RF switches, each comprising:
• first and second control inputs;
• first, second and third DC blocking capacitors each having first and second terminals;
• first, second and third RF I/O ports, coupled respectively to the first terminals of the first, second and third DC blocking capacitors, wherein the first RF I/O ports of the at least two otherwise independent RF switches are coupled together in parallel;
• a first enhancement mode multi-gate FET device having source, drain and gate terminals, wherein its source terminal is coupled to the second terminal of the first DC blocking capacitor, its drain terminal is coupled to the second terminal of the second DC blocking capacitor and its gate terminals are coupled to the first control input;
• a second enhancement mode multi-gate FET device having source, drain and gate terminals, wherein its source terminal is coupled to the second terminal of the first DC blocking capacitor, its drain terminal is coupled to the second terminal of the third DC blocking capacitor and its gate terminals are coupled to the second control input;
• and
• first and second bias resistances Rb, Rb′, each having first and second terminals, wherein the first bias resistor Rb has its first terminal coupled to the second terminal of the first DC blocking capacitor and its second terminal coupled to the first control input, and the second bias resistor Rb′ has its first terminal coupled to the second terminal of the first DC blocking capacitor and its second terminal coupled to the second control input.