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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHung-Wei Chen, Hsun-Chih Tsao, Kuang-Hsin Chen, Di-Hong Lee
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A semiconductor device and method for forming the same including improved electrostatic discharge protection for advanced semiconductor devices, the semiconductor device including providing semiconductor substrate having a pre-selected surface orientation and crystal direction; an insulator layer overlying the semiconductor substrate; a first semiconductor active region overlying the insulator layer having a first surface orientation selected from the group consisting of <100> and <110>; a second semiconductor active region extending through a thickness portion of the insulator layer having a second surface orientation selected from the group consisting of <110> and <100> different from the first surface orientation; wherein MOS devices including a first MOS device of a first conduction type is disposed on the first semiconductor active region and a second MOS device of a second conduction type is disposed on the second semiconductor active region.
A semiconductor device comprising:
The semiconductor device of claim 11, wherein the multiple gate structures are selected from the group consisting of a FinFET gate structure and a triple gate structure.
The semiconductor device of claim 19, wherein the second semiconductor active regions extend through a thickness portion of the insulator layer.
A method of forming a semiconductor device comprising:
The method of claim 22, wherein the first and second semiconductor active regions comprise respective strained channel regions.
The method of claim 23, wherein the strained channel regions comprises a strain primarily in a source to drain direction.
The method of claim 22, wherein the second semiconductor active region is formed in electrical communication with the semiconductor substrate for receiving a portion of an electrostatic discharge signal.
The method of claim 22, wherein the semiconductor substrate and the first and second semiconductor active regions comprise silicon.
The method of claim 22, wherein the first semiconductor active region has a surface orientation of (100) and the second semiconductor active region has a surface orientation of (110).
The method of claim 22, wherein the first semiconductor active region has a surface orientation of (110) and the second semiconductor active region has a surface orientation of (100).
The method of claim 22, wherein a NMOS device is formed on the first semiconductor active region and a PMOS device is formed on the second semiconductor active region.
The method of claim 22, wherein a PMOS device is formed on the first semiconductor active region and a NMOS device is formed on the second semiconductor active region.
The method of claim 22, further comprising forming at least one stressed dielectric layer over at least one of the first and second MOS devices to form a respective strained channel region.
The method of claim 22, wherein the MOS devices comprise multiple gate structures.
The method of claim 32, wherein the multiple gate structures are selected from the group consisting of a FinFET gate structure and a triple gate structure.
The method of claim 36, wherein the insulator layer comprises a buried oxide layer.
The method of claim 38, wherein the underlying insulator region comprises a buried oxide (BOX) region formed in a bottom portion of the first and second semiconductor active regions.
The method of claim 38, wherein both the first and second semiconductor active regions are electrically isolated from the semiconductor substrate by respective underlying insulator regions.
The method of claim 40, wherein the first and second semiconductor active regions extend through a thickness portion of the insulator layer.
The method of claim 41, wherein the second semiconductor active region is formed for receiving a portion of an electrostatic discharge signal.
Dependencies are inferred from the claim text.