Ballistic direct injection NROM cell on strained silicon structures

A nitride read only memory device comprising:

• control circuitry that controls operation of the integrated circuit;
• and
• a memory array, coupled to the control circuitry, the memory array comprising a plurality of memory cells, each cell comprising:
• a silicon-germanium layer comprising a pair of source/drain regions;
• a strained silicon layer formed overlying the silicon-germanium layer and comprising a channel region between the pair of source/drain regions;
• a split gate nitride layer comprising a pair of charge storage regions;
• and
• a control gate formed overlying the nitride layer and comprising a depression formed between the pair of charge storage regions that splits the nitride layer such that the pair charge storage regions are electrically isolated from each other.

A nitride read only memory device comprising:

• control circuitry that controls operation of the integrated circuit;
• and
• a memory array, coupled to the control circuitry, the memory array comprising a plurality of memory cells, each cell comprising:
• a pillar in a silicon-germanium layer, the pillar being defined by a plurality of trenches;
• a pair of source/drain regions, each source/drain region located under a different trench;
• a strained silicon layer formed overlying the silicon-germanium layer at the top of each pillar and comprising a channel region between the pair of source/drain regions;
• a pair of vertical nitride charge storage regions that are separated by the pillar and insulated from the pillar by a first dielectric layer;
• and
• a control gate formed overlying the pair of vertical charge storage regions and the pillar and insulated from the vertical charge storage regions and the pillar by a second dielectric layer.

A method for fabricating a nitride read only memory array, the method comprising:

• forming a silicon-germanium layer on a substrate, the silicon-germanium layer comprising a plurality of pairs of source/drain regions;
• forming a strained silicon layer over the silicon-germanium layer;
• forming a first dielectric layer over the strained silicon layer;
• forming a plurality of nitride layers, each layer over the strained silicon layer and substantially between each pair of source/drain regions;
• forming a second dielectric layer over each nitride layer;
• and
• forming a control gate over each nitride layer.

A method for fabricating a split gate nitride read only memory array, the method comprising:

• forming a silicon-germanium layer on a silicon substrate;
• forming a plurality of pillars in the silicon-germanium layer such that a trench is formed between each pair of pillars,
• forming a source/drain region under each trench;
• forming a strained silicon layer at the top of each pillar;
• forming a dielectric layer over each pillar and in each trench;
• forming an oxide-nitride-oxide layer along each pillar sidewall;
• and
• forming a control gate over the dielectric layer on each pillar and in each trench between adjacent oxide-nitride-oxide layers.

A method for fabricating a split gate nitride read only memory array, the method comprising:

• forming a silicon-germanium layer on a silicon substrate, the silicon-germanium layer comprising a plurality of pairs of source/drain regions;
• forming a strained silicon layer overlying the silicon-germanium layer, , each pair of source/drain regions linked by a channel region in the strained silicon layer;
• forming an oxide-nitride-oxide composite layer, comprising a pair of charge storage regions, over the strained silicon layer;
• and
• forming a control gate overlying the composite layer.