Non-volatile memory device for 2-bit operation and method of fabricating the same

A non-volatile memory device for 2-bit operation comprising:

• active regions formed in a first zigzag pattern to extend in a word line direction in a semiconductor substrate, and partially to be bent repeatedly;
• gates formed in a second zigzag pattern to extend in a word line direction in the semiconductor substrate, partially to cross with the active regions, and to be bent repeatedly in symmetry with the first zigzag pattern;
• a charge storage layer disposed below the gate, and confined at a portion where the gate and the active regions cross;
• a charge blocking layer formed at an interface between the charge storage layer and the gate;
• a tunnel dielectric layer formed at an interface between the charge storage layer and the active regions;
• first and second source/drain regions formed at an exposed portion out of both sides of the gate in the active regions;
• and
• first and second bit lines connected to the first and second source/drain regions respectively, and formed to extend in a bit line direction crossing the word line direction.

A non-volatile memory device for 2-bit operation comprising:

• active regions formed in a zigzag pattern and formed to extend in a word line direction in a semiconductor substrate and partially to be bent repeatedly;
• gates formed in a straight pattern and formed to extend in a word line direction on the semiconductor substrate and partially to cross the active regions repeatedly;
• a charge storage layer disposed below the gate, and confined at a portion where the gate and the active regions cross;
• a charge blocking layer formed at an interface between the charge storage layer and the gate;
• a tunnel dielectric layer formed at an interface between the charge storage layer and the active regions;
• first and second source/drain regions formed at an exposed portion out of both sides of the gate in the active regions;
• and
• first and second bit lines connected to the first and second source/drain regions respectively, and formed to extend in a bit line direction crossing the word line direction.

A non-volatile memory device for 2-bit operation comprising:

• active regions formed in a straight pattern and formed to extend in a word line direction in a semiconductor substrate;
• gates formed in a zigzag pattern and formed to extend in a word line direction on the semiconductor substrate and partially to cross the active regions repeatedly, and to be bent repeatedly;
• a charge storage layer disposed below the gate, and confined at a portion where the gate and the active regions cross;
• a charge blocking layer formed at an interface between the charge storage layer and the gate;
• a tunnel dielectric layer formed at an interface between the charge storage layer and the active regions;
• first and second source/drain regions formed at an exposed portion out of both sides of the gate in the active regions;
• and
• first and second bit lines connected to the first and second source/drain regions respectively, and formed to extend in a bit line direction crossing the word line direction.

A method of fabricating a non-volatile memory for 2-bit operation comprising:

• sequentially forming a tunnel dielectric layer, a charge storage layer, and a charge blocking layer on a-semiconductor substrate;
• forming a hard mask for an isolation region defining active regions with a first zigzag pattern extending in a word line direction on the charge blocking layer, and partially being bent repeatedly;
• sequentially patterning the tunnel dielectric layer, the charge storage layer, and the charge blocking layer, using the hard mask as an etch mask;
• forming the isolation region in the semiconductor substrate exposed to the hard mask;
• selectively removing the hard mask;
• forming gates in a second zigzag pattern on the patterned charge blocking layer to extend in a word line direction on the semiconductor substrate, and partially to cross with the active regions repeatedly and repeatedly to be bent in symmetry with the first zigzag pattern;
• selectively removing the underneath exposed and remaining charge blocking layer, the charge storage layer and the tunnel dielectric layer using the gate as an etch mask, thereby patterning such that the charge storage layer is confined to the portions where the gate and the active cross;
• forming first and second source/drain regions in the active region at a region exposed out of both sides of the gate;
• forming an insulating layer to cover the first and second source/drain regions and the gate;
• forming a connecting contact penetrating the insulating layer and exposing the first and second source/drain regions;
• and
• forming first and second bit lines on the insulating layer to be connected to the first and second source/drain regions respectively through the connecting contact and extend in a bit line direction crossing the word line direction.

A method of fabricating a non-volatile memory device for 2-bit operation comprising:

• sequentially forming a tunnel dielectric layer, a charge storage layer, and a charge blocking layer on a semiconductor substrate;
• forming a hard mask for an isolation region defining active regions defined as a zigzag pattern extending in a word line direction on the charge blocking layer and partially being bent repeatedly;
• sequentially patterning the tunnel dielectric layer, the charge storage layer, and the charge blocking layer using the hard mask as an etch mask;
• forming the isolation region on the semiconductor substrate portion exposed to the hard mask;
• selectively removing the hard mask;
• forming gates of a straight pattern extending in a word line direction on the patterned charge blocking layer and partially crossing with the active regions repeatedly;
• selectively removing the underneath remaining charge blocking layer, the charge storage layer, and the tunnel dielectric layer portion using the gate as an etch mask, thereby patterning to confine the charge storage layer at a portion where the gate and the active regions cross;
• forming first and second source/drain regions at a portion exposed out of both sides of the gate in the active;
• forming an insulating layer covering the first and second source/drain regions and the gate;
• forming a connecting contact penetrating the insulating layer and exposing the first and second source/drain regions;
• and
• forming first and second bit lines on the insulating layer to be connected to the first and second source/drain regions respectively through the connecting contact and extend in a bit line direction crossing with the word line direction.

A method of fabricating a non-volatile memory device for 2-bit operation comprising:

• sequentially forming a tunnel dielectric layer, a charge storage layer, and a charge blocking layer on a semiconductor substrate;
• forming a hard mask for an isolation region defining active regions defined as a straight pattern extending in a word line direction on the charge blocking layer;
• sequentially patterning the tunnel dielectric layer, the charge storage layer, and the charge blocking layer using the hard mask as an etch mask;
• forming the isolation region on the semiconductor substrate portion exposed to the hard mask;
• selectively removing the hard mask;
• forming gates of a zigzag pattern extending in a word line direction on the patterned charge blocking layer, partially crossing with the active regions repeatedly, and partially being bent repeatedly;
• selectively removing the underneath remaining charge blocking layer, the charge storage layer, and the tunnel dielectric layer portion using the gate as an etch mask, thereby patterning to confine the charge storage layer at a portion where the gate and the active regions cross;
• forming first and second source/drain regions at a portion exposed out of both sides of the gate in the active regions;
• forming an insulating layer covering the first and second source/drain regions and the gate;
• forming a connecting contact penetrating the insulating layer and exposing the first and second source/drain regions;
• and
• forming first and second bit lines on the insulating layer to be connected to the first and second source/drain regions respectively through the connecting contact and extend in a bit line direction crossing with the word line direction.