High density semiconductor memory and method of making
AssigneeMicron Technology, Inc.
InventorDaniel Doyle
Life of this patent
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Abstract
A memory cell, array and device include cross-shaped active areas and polysilicon gate areas disposed over arm portions of adjacent cross-shaped active areas. The polysilicon gate areas couple word lines with capacitors associated with each arm portion of the cross-shaped active areas. Buried digit lines are coupled to body portions of the cross-shaped active areas. The word lines and digit lines provide a unique contact to each capacitor of the array of memory cells. Each memory cell has an area of 5 F2. An electronic system and method for fabricating a memory cell are also disclosed.
Claims50
An array of DRAM cells, comprising:
- a plurality of cross-shaped active areas, each cross-shaped active area having a plurality of arm portions and a body portion;
- a polysilicon gate area disposed over one arm portion of the plurality of arm portions of at least some of the plurality of cross-shaped active areas;
- at least one capacitor electrically coupled to the polysilicon gate area;
- a buried digit line electrically coupled to a body portion of at least one cross-shaped active area;
- and
- a buried word line positioned substantially orthogonally to the buried digit line and electrically coupled with the polysilicon gate area.
An array of DRAM cells, comprising:
- a plurality of cross-shaped active areas, each cross-shaped active area having four associated capacitors;
- a plurality of polysilicon gate areas, each polysilicon gate area disposed over a portion of four of the plurality of cross-shaped active areas and electrically coupled with one associated capacitor of each of the four cross-shaped active areas;
- a buried digit line electrically coupled to at least one cross-shaped active area;
- and
- a buried word line positioned substantially orthogonally to the buried digit line and electrically coupled to at least one polysilicon gate area.
An electronic system, comprising:
- a processor having a processor bus;
- an input device coupled to the processor through the processor bus and adapted to allow data to be input to the electronic system;
- an output device coupled to the processor through the processor bus and adapted to allow data to be output from the electronic system;
- and
- a memory device coupled to the processor through the processor bus, the memory device comprising:
- a memory array, comprising:
- a plurality of cross-shaped active areas, each cross-shaped active area having a plurality of arm portions and a body portion;
- a polysilicon gate area disposed over one arm portion of the plurality of arm portions of at least some of the plurality of cross-shaped active areas;
- at least one capacitor electrically coupled the polysilicon gate area;
- a buried digit line electrically coupled to a body portion of at least one cross-shaped active area;
- and
- a buried word line positioned substantially orthogonally to the buried digit line and electrically coupled with the polysilicon gate area.
A method of forming a plurality of memory cells on a surface of a substrate, comprising:
- forming at least one cross-shaped active area having a plurality of arms in the substrate;
- forming a like plurality of capacitors, each capacitor associated with an arm of the at least one cross-shaped active area;
- disposing a polysilicon gate area over an arm of the plurality of arms;
- forming a buried digit line electrically coupled to a portion of the at least one cross-shaped active area;
- and
- forming a buried word line electrically coupled to the polysilicon gate area.
A DRAM cell having an area of 5 F2.
Dependencies are inferred from the claim text.