A data receiver coupled to received data at a data bus port, the data receiver comprising:
- a clock generator generating a receive clock signal, the clock generator including a phase adjust input to adjust the phase of the receive clock signal responsive to a phase adjust signal applied to the phase adjust input;
- an expected pattern memory storing an expected data pattern;
- a receive capture buffer coupled to the data bus port, the receive capture buffer being operable to capture data coupled to the data bus port, including a plurality of sequentially received data patterns;
- a pattern comparator coupled to the receive capture buffer and to the expected pattern memory, the pattern comparator being operable to compare the captured data patterns to the expected data pattern stored in the expected pattern memory and to generate a results signal indicative of the results of each of the comparisons;
- phase adjustment logic coupled to the receive clock generator and to the pattern comparator to receive the results signal from the pattern comparator, the phase adjustment logic being operable to output the phase adjust signal;
- and
- a receive interface controller coupled to the pattern comparator and to the phase adjustment logic, the receiver interface controller being operable in an initialization mode to cause the phase adjustment logic to sequentially output a plurality of phase adjust signals to cause the receive clock generator to incrementally alter the phase of the receive clock signal to allow the receive interface controller to determine based on the results signal from the pattern comparator the phases of the receive clock signal that are able to capture received data patterns that match the expected data pattern stored in the expected pattern memory, the receive interface controller further being operable to determine a final value for the phase of the receive clock signal based on the determination of the phases of the receive clock signal that are able to capture received data patterns that match the expected data pattern, the receive interface controller being operable in a normal operating mode to cause the phase adjustment logic to output a phase adjust signal that causes the receive clock generator to set the phase of the receive clock signal to the final phase value.