Control system
AssigneeFanuc Corporation
InventorsKazunari Aoyama, Kunitaka Komaki, Minoru Nakamura, Takaaki Komatsu
Life of this patent
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Abstract
A transmission path delay is set in a shift setting register. A slave unit generates a PRE_ITP signal in response to a timing signal (ITP signal) issued by a master unit. The phase difference between this PRE_ITP signal and the ITP signal unique to the slave unit is loaded into a period modification counter. A timer corrects a reference value, outputs position/speed control period signals (SYN signals) and counts down the period modification counter with these SYN signals until the period modification counter reaches zero. Furthermore, the ITP signal unique to the slave unit is outputted every time a predetermined number of the SYN signals are outputted.
Claims7
A control system in which a single control apparatus serving as a master unit and one or more control apparatuses serving as slave units are connected by a serial bus, for performing synchronous control of motors that are controlled by these different control apparatuses,
- wherein each slave unit comprises correcting means which obtains a phase difference between a timing signal transmitted by said master unit and received by said slave unit, and a timing signal generated by said slave unit, which obtains, from said phase difference, a correction amount for aligning said slave unit side timing signal with said master unit side timing signal, and which corrects a timing signal generation period of said slave unit in accordance with said correction amount,
- whereupon said timing signal corrected by said correcting means is outputted.
Dependencies are inferred from the claim text.