Symmetric multiprocessor operating system for execution on non-independent lightweight thread context
AssigneeMIPS Technologies, Inc.
InventorKevin Kissell
Life of this patent
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AssigneeMIPS Technologies, Inc.
InventorKevin Kissell
Estimating the term…
A multiprocessing system is disclosed. The system includes a multithreading microprocessor having a plurality of thread contexts (TCs), a translation lookaside buffer (TLB) shared by the plurality of TCs, and an instruction scheduler, coupled to the plurality of TCs, configured to dispatch to execution units, in a multithreaded fashion, instructions of threads executing on the plurality of TCs. The system also includes a multiprocessor operating system (OS), configured to schedule execution of the threads on the plurality of TCs, wherein a thread of the threads executing on one of the plurality of TCs is configured to update the shared TLB, and prior to updating the TLB to disable interrupts, to prevent the OS from unscheduling the TLB-updating thread from executing on the plurality of TCs, and disable the instruction scheduler from dispatching instructions from any of the plurality of TCs except from the one of the plurality of TCs on which the TLB-updating thread is executing.
A multiprocessing system, comprising:
A method for a multiprocessor operating system (OS) to run on a multiprocessing system including a multithreading microprocessor having a plurality of thread contexts (TCs), a translation lookaside buffer (TLB) shared by the plurality of TCs, and an instruction scheduler configured to dispatch to execution units instructions of threads executing on the plurality of TCs in a multithreaded fashion, the method comprising:
A computer program product for use with a computing device, the computer program product comprising:
A method for providing operating system software for running on a multiprocessing system including a multithreading microprocessor having a plurality of thread contexts (TCs), a translation lookaside buffer (TLB) shared by the plurality of TCs, and an instruction scheduler configured to dispatch to execution units instructions of threads executing on the plurality of TCs in a multithreaded fashion, the method comprising:
Dependencies are inferred from the claim text.