Methods and apparatus for implementing parameterizable processors and peripherals

A method for implementing a programmable chip, the method comprising:

• receiving a processor core design associated with the programmable chip, the processor core design being parameterizable;
• identifying a processor core parameter associated with the processor core design;
• receiving a peripheral design associated with the programmable chip, the peripheral design being parameterizable;
• and
• generating a logic description using the processor core parameter and the peripheral design, wherein the logic description provides logic information for implementing the processor core and the peripheral on the programmable chip.

A method for implementing a programmable chip, the method comprising:

• receiving a processor core design associated with the programmable chip, the processor core design being parameterizable;
• receiving a peripheral design associated with the programmable chip, the peripheral design being parameterizable;
• identifying a peripheral parameter associated with the peripheral design;
• generating a logic description using the processor core design and the peripheral parameter, wherein the logic description provides logic information for implementing the processor core and the peripheral on the programmable chip.