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US 2006/0190906 A1Published application
Efficient method for mapping a logic design on field programmable gate arrays
OwnerDhabalendu Samanta, Viren Agarwalinventors
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Abstract
An efficient method for mapping a logic design on Field Programmable Gate Arrays involves a determination of the minimum required square grid of FPGA logic blocks for mapping the design, providing a compensation factor on the minimum square grids, selecting the maximum value among the compensated square grids for reducing the mapping time; and implementing a legalization adjustment to ensure mapping of said compensated design.
Claims9
An efficient method for mapping a logic design on Field Programmable Gate Arrays comprising:
- determining the minimum required square grid of FPGA logic blocks for mapping said design;
- providing a compensation factor on said minimum square grids, and selecting the maximum value amongst said compensated square grids for reducing the placement time;
- and
- implementing a legalization adjustment to ensure mapping of said compensated design.
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Dependencies are inferred from the claim text.