Method, system and computer program product for automatically estimating pin locations and interconnect parasitics of a circuit layout

A circuit design system comprising:

• means for automatically estimating lengths of interconnect segments to be employed in interconnecting at least some circuit components of a plurality of placed circuit components of a circuit layout, the means for automatically estimating including means for automatically generating pin locations for a plurality of pins to be employed with the at least some circuit components of the circuit layout, the interconnect segments to interconnect the plurality of pins, and means for employing a route estimator to estimate lengths of the interconnect segments based on the generated pin locations of the plurality of pins;
• and
• means for employing the estimated interconnect segments lengths to automatically estimate resistance capacitance interconnect parasitics for the interconnect segments to be employed in the circuit layout.

At least one program storage device readable by a machine embodying at least one program of instructions executable by the machine to perform a circuit design method, the method comprising:

• automatically estimating lengths of interconnect segments to be employed in interconnecting at least some circuit components of a plurality of placed circuit components of a circuit layout, the automatically estimating including automatically generating pin locations for a plurality of pins to be employed with the at least some circuit components of the circuit layout, the interconnect segments to interconnect the plurality of pins, and employing a route estimator to estimate lengths of the interconnect segments based on the generated pin locations of the plurality of pins;
• and
• employing the estimated interconnect segment lengths in automatically estimating resistance capacitance interconnect parasitics for the interconnect segments to be employed in the circuit layout.