Method of clock tree distribution generation by determining allowed placement regions for clocked elements

A method of generating allowable placement regions in a clock distribution network of an integrated circuit (IC) chip comprising the steps of:

• a) allocating the entire IC chip area to an allowable placement region of at least one clock tree leaf element having at least one non-clock port;
• b) determining a sub-region associated with at least one of said non-clock ports of said clock tree leaf element;
• c) redefining said clock tree leaf element allowable placement region to be an intersection of said clock tree leaf element allowable placement region with said sub-region;
• d) generating a list of congested regions and subtracting congested regions from said allowable placement region;
• and
• e) generating a list of blockage regions and subtracting blockage regions from said allowable placement region.

A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for generating a clock distribution network on an integrated circuit, said method steps comprising:

• determining an allowable placement region for each of at least one clock tree leaf element;
• grouping said at least one clock tree leaf element into at least one cluster;
• and
• placing said at least one clock tree leaf element at a location within said allowable placement region wherein a cost function is minimized.