Methods of routing an integrated circuit design
AssigneeCadence Design Systems, Inc.
InventorsLimin He, So-Zen Yao, Wenyong Deng, Jing Chen, Liang-Jih Chao
Life of this patent
Estimating the term…
Abstract
An innovative routing method for an integrated circuit design layout. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
Claims24
1-26. (canceled)
A method of routing an integrated circuit (IC) design, comprising:
- accessing the IC design including a plurality of blockages and a plurality of pins;
- forming a first graph including a first plurality of nodes, wherein
- each node of the first plurality of nodes is formed outside every blockage of the plurality of blockages;
- and
- interconnecting the plurality of pins through nodes of the first graph.
30-56. (canceled)
A method of routing an integrated circuit (IC) design, comprising:
- accessing the IC design including a plurality of objects;
- accessing a plurality of routing algorithms;
- interconnecting, with a first plurality of interconnections, one or more of the plurality of objects, at least partly in response to a first combination of one or more routing algorithms of the plurality of routing algorithms;
- and
- storing the first plurality of interconnections.
A method of routing an integrated circuit (IC) design, comprising:
- interconnecting at least a first portion of the IC design at a first routing pitch;
- and
- if the interconnecting results in one or more design rule violations, routing at least a part of the first portion of the IC design at a second routing pitch different than the first routing pitch.
64-69. (canceled)
Dependencies are inferred from the claim text.