Method and program for designing semiconductor device
AssigneeNEC Electronics Corporation
InventorHirotaka Ishikawa
Life of this patent
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Abstract
A method for designing a semiconductor device by using a computer, includes steps (a) to (b). The step (a) is the step of placing a power line and a ground line along a first direction. The step (b) is the step of placing a capacity cell which includes a bypass capacitor connected between the power line and the ground line. The step (b) includes (b1) placing plural kinds of element cells along a second direction perpendicular to the first direction. The capacity cell is composed of the plural kinds of element cells.
Claims20
A method for designing a semiconductor device by using a computer, comprising:
- (a) placing a power line and a ground line along a first direction;
- and
- (b) placing a capacity cell which includes a bypass capacitor connected between said power line and said ground line,
- wherein said step (b) includes:
- (b1) placing plural kinds of element cells along a second direction perpendicular to said first direction, said capacity cell is composed of said plural kinds of element cells.
A computer program product, which includes a method for designing a semiconductor device, embodied on a computer-readable medium and comprising code that, when executed, causes a computer to perform the following:
- (a) placing a power line and a ground line along a first direction;
- and
- (b) placing a capacity cell which is connected between said power line and said ground line, and includes a bypass capacitor,
- wherein said step (b) includes:
- (b1) placing plural kinds of element cells along a second direction perpendicular to said first direction, said capacity cell is composed of said plural kinds of element cells.
A semiconductor device designing apparatus comprising:
- a first storage unit configured to store data indicating plural kinds of element cells;
- a processing unit configured to electrically connected to said storage unit;
- and
- a second storage unit configured to store a design program which is executed by said processing unit,
- wherein a capacity cell, which is composed of said plural kinds of element cells, includes a bypass capacitor connected between said power line and said ground line,
- said power line and said ground line are placed along a first direction, and
- said processing unit reads out said data and places said plural kinds of element cells along a second direction perpendicular to said first direction.
A semiconductor device comprising:
- a logic device configured to be formed in an area between a first line and a second line parallel to said first line;
- a first power supply line configured to be formed larger than said area;
- a second power supply line configured to be formed larger than said area;
- and
- a bypass capacitor configured to electrically connect said first power supply line and said second power supply line,
- wherein said bypass capacitor includes a contact which is connected to one of said first power supply line and said second power supply line, said contact is formed in said area such that said contact does not overlap said first line and said second line.
Dependencies are inferred from the claim text.